From 596a19feaee79f725de70c16f9b188369d0322b9 Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Sat, 3 May 2025 21:39:03 -0400 Subject: Parity testbench --- pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'pb_APP_log_comb.srcs/sim_1/imports/verif') diff --git a/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd index 79fffad..39a5819 100644 --- a/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd +++ b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd @@ -34,8 +34,8 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; -- requis pour enoncés de type mem_valeurs_tests(to_integer( unsigned(table_valeurs_adr(9 downto 6) ))); -use ieee.numeric_std.ALL; -- -use IEEE.STD_LOGIC_UNSIGNED.ALL; -- +use ieee.numeric_std.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; entity AppCombi_top_tb is @@ -202,9 +202,9 @@ begin resultat_attendu <= vecteur_test_sim(13 downto 9); -- Assignation of variables to add4bit - add_a_sim <= vecteur_test_sim(8 downto 5); - add_b_sim <= vecteur_test_sim(4 downto 1); - add_cin_sim <= vecteur_test_sim(0); + add_a_sim <= vecteur_test_sim(8 downto 5); + add_b_sim <= vecteur_test_sim(4 downto 1); + add_cin_sim <= vecteur_test_sim(0); wait for delai_sim; -- cgit v1.2.3