From 1b8b70ea0d1f1dd79a1b1f1a1b05208bb8c1ca30 Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Sat, 3 May 2025 12:52:42 -0400 Subject: Add4Bits works mothaflacka --- pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'pb_APP_log_comb.srcs/sources_1/imports/src') diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd index 79209c9..b9be1dc 100644 --- a/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd +++ b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd @@ -56,10 +56,10 @@ architecture BEHAVIORAL of AppCombi_top is component Add4Bits is Port ( - A : in STD_LOGIC_VECTOR (0 to 3); - B : in STD_LOGIC_VECTOR (0 to 3); + A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); C : in STD_LOGIC; - R : out STD_LOGIC_VECTOR (0 to 3); + R : out STD_LOGIC_VECTOR (3 downto 0); Rc : out STD_LOGIC ); end component; @@ -114,6 +114,13 @@ begin o_pmodled <= d_opa & d_opb; -- Les opérandes d'entrés reproduits combinés sur Pmod8LD o_led (3 downto 0) <= '0' & '0' & '0' & d_S_1Hz; -- La LED0 sur la carte représente la retenue d'entrée +adder4 : Add4Bits port map ( + A => d_opa, + B => d_opb, + C => d_cin, + R => d_sum, + Rc => d_cout +); end BEHAVIORAL; -- cgit v1.2.3