From 0bfa029ee6c5bdbc6d5601b3200d7367fcea02ba Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Thu, 1 May 2025 09:15:23 -0400 Subject: Batman --- pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd | 49 +++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd (limited to 'pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd') diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd new file mode 100644 index 0000000..0b1ed7c --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd @@ -0,0 +1,49 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/30/2025 03:19:19 PM +-- Design Name: +-- Module Name: Add1BitA - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Add1BitA is + Port ( X : in STD_LOGIC; + Y : in STD_LOGIC; + Ci : in STD_LOGIC; + O : out STD_LOGIC; + Co : out STD_LOGIC); +end Add1BitA; + +architecture Behavioral of Add1BitA is + +begin + + O <= (X xor Y) xor Ci; + Co <= ((X xor Y) and Ci) or (X and Y); + +end; -- cgit v1.2.3