From 0bfa029ee6c5bdbc6d5601b3200d7367fcea02ba Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Thu, 1 May 2025 09:15:23 -0400 Subject: Batman --- pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd | 47 +++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd (limited to 'pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd') diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd new file mode 100644 index 0000000..be2cf13 --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd @@ -0,0 +1,47 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/30/2025 03:19:19 PM +-- Design Name: +-- Module Name: Add4Bits - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Add4Bits is + Port ( X : in STD_LOGIC_VECTOR (0 to 3); + Y : in STD_LOGIC_VECTOR (0 to 3); + Ci : in STD_LOGIC; + O : out STD_LOGIC_VECTOR (0 to 3); + Co : out STD_LOGIC); +end Add4Bits; + +architecture Behavioral of Add4Bits is + +begin + + +end Behavioral; -- cgit v1.2.3