From 1b8b70ea0d1f1dd79a1b1f1a1b05208bb8c1ca30 Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Sat, 3 May 2025 12:52:42 -0400 Subject: Add4Bits works mothaflacka --- pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd') diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd index 371d81b..71c09d9 100644 --- a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd +++ b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd @@ -32,10 +32,10 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; entity Add4Bits is - Port ( A : in STD_LOGIC_VECTOR (0 to 3); - B : in STD_LOGIC_VECTOR (0 to 3); + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); C : in STD_LOGIC; - R : out STD_LOGIC_VECTOR (0 to 3); + R : out STD_LOGIC_VECTOR (3 downto 0); Rc : out STD_LOGIC); end Add4Bits; -- cgit v1.2.3