From 0747a69b0cb0be8b8abd017684b251013b23e11e Mon Sep 17 00:00:00 2001 From: LYAM Date: Sat, 3 May 2025 17:31:12 -0400 Subject: unit test add 4 bit, Fix Add1bitB --- pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd') diff --git a/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd b/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd index e0cb89c..470e7c4 100644 --- a/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd +++ b/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd @@ -35,13 +35,14 @@ use IEEE.STD_LOGIC_1164.ALL; entity Fct_2_3 is Port ( ADCbin : in STD_LOGIC_VECTOR (3 downto 0); - A2_3 : out STD_LOGIC_VECTOR (2 downto 0)); + A2_3 : out STD_LOGIC_VECTOR (3 downto 0)); end Fct_2_3; architecture Behavioral of Fct_2_3 is signal shifted_once : STD_LOGIC_VECTOR(3 downto 0); signal shifted_twice : STD_LOGIC_VECTOR(3 downto 0); signal shifted_thrice : STD_LOGIC_VECTOR(3 downto 0); + signal carry_out : STD_LOGIC; component Add4Bits is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); @@ -52,16 +53,18 @@ architecture Behavioral of Fct_2_3 is end component; begin -- N x 2^-1 : shifted once - shifted_once <= '0' & ADCbin(3 downto 0); + shifted_once <= '0' & ADCbin(3 downto 1); -- N x 2^-3 : shifted thrice - shifted_twice <= '0' & shifted_once(3 downto 0); - shifted_thrice <= '0' & shifted_twice(3 downto 0); + shifted_twice <= '0' & shifted_once(3 downto 1); + shifted_thrice <= '0' & shifted_twice(3 downto 1); -- Both are then added to give the result of the 2/3 multiplication (0.625) result : Add4Bits port map ( - X => shifted_once, - Y => shifted_thrice, - O => A2_3 + A => "0110", + B => "0001", + C => '0', + R => A2_3, + Rc => carry_out ); end Behavioral; -- cgit v1.2.3