From 4bd43e9bd0dc5cb27df985bf171b77f3e1b6da21 Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Mon, 5 May 2025 10:52:25 -0400 Subject: Minus_5 Testbench --- pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd') diff --git a/pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd b/pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd index 977bac1..065bd1f 100644 --- a/pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd +++ b/pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd @@ -31,9 +31,9 @@ use IEEE.STD_LOGIC_1164.ALL; --library UNISIM; --use UNISIM.VComponents.all; -entity Moins_5 is - Port ( Moins5 : out STD_LOGIC_VECTOR (3 downto 0); - ADCbin : in STD_LOGIC_VECTOR (3 downto 0)); +entity Moins_5 is Port ( + ADCbin : in STD_LOGIC_VECTOR (3 downto 0); + Moins5 : out STD_LOGIC_VECTOR (3 downto 0)); end Moins_5; -- cgit v1.2.3