From 0bfa029ee6c5bdbc6d5601b3200d7367fcea02ba Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Thu, 1 May 2025 09:15:23 -0400 Subject: Batman --- pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd (limited to 'pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd') diff --git a/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd b/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd new file mode 100644 index 0000000..7f5148d --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd @@ -0,0 +1,54 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/30/2025 01:11:03 PM +-- Design Name: +-- Module Name: full_adder - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity full_adder is + Port ( c_in : in STD_LOGIC; + a : in STD_LOGIC; + b : in STD_LOGIC; + o : out STD_LOGIC; + c_o : out STD_LOGIC); +end full_adder; + +architecture Behavioral of full_adder is + + signal aXb : STD_LOGIC; + +begin + + aXb <= a xor b; + + o <= aXb xor c_in; + c_o <= (aXb and c_in) or (a and b); + + +end Behavioral; -- cgit v1.2.3