From 1b8b70ea0d1f1dd79a1b1f1a1b05208bb8c1ca30 Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Sat, 3 May 2025 12:52:42 -0400 Subject: Add4Bits works mothaflacka --- pb_APP_log_comb.srcs/sources_1/new/is_even.vhd | 49 ++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 pb_APP_log_comb.srcs/sources_1/new/is_even.vhd (limited to 'pb_APP_log_comb.srcs/sources_1/new/is_even.vhd') diff --git a/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd b/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd new file mode 100644 index 0000000..53eb4dc --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd @@ -0,0 +1,49 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 05/03/2025 12:04:25 PM +-- Design Name: +-- Module Name: is_even - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity is_even is + Port ( x : in STD_LOGIC_VECTOR (3 downto 0); + o : out STD_LOGIC); +end is_even; + +architecture Behavioral of is_even is + + signal y : STD_LOGIC_VECTOR (0 to 1); + +begin + + y(0) <= x(0) xor x(1); + y(1) <= x(2) xor x(3); + o <= y(0) xor y(1); + +end Behavioral; -- cgit v1.2.3