From 1b8b70ea0d1f1dd79a1b1f1a1b05208bb8c1ca30 Mon Sep 17 00:00:00 2001
From: Benjamin Chausse <benjamin@chausse.xyz>
Date: Sat, 3 May 2025 12:52:42 -0400
Subject: Add4Bits works mothaflacka

---
 pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd |  6 +--
 pb_APP_log_comb.srcs/sources_1/new/is_even.vhd  | 49 +++++++++++++++++++++++++
 2 files changed, 52 insertions(+), 3 deletions(-)
 create mode 100644 pb_APP_log_comb.srcs/sources_1/new/is_even.vhd

(limited to 'pb_APP_log_comb.srcs/sources_1/new')

diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
index 371d81b..71c09d9 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
@@ -32,10 +32,10 @@ use IEEE.STD_LOGIC_1164.ALL;
 --use UNISIM.VComponents.all;
 
 entity Add4Bits is
-    Port ( A : in STD_LOGIC_VECTOR (0 to 3);
-           B : in STD_LOGIC_VECTOR (0 to 3);
+    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
+           B : in STD_LOGIC_VECTOR (3 downto 0);
            C : in STD_LOGIC;
-           R : out STD_LOGIC_VECTOR (0 to 3);
+           R : out STD_LOGIC_VECTOR (3 downto 0);
            Rc : out STD_LOGIC);
 end Add4Bits;
 
diff --git a/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd b/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd
new file mode 100644
index 0000000..53eb4dc
--- /dev/null
+++ b/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd
@@ -0,0 +1,49 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 05/03/2025 12:04:25 PM
+-- Design Name:
+-- Module Name: is_even - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity is_even is
+    Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
+           o : out STD_LOGIC);
+end is_even;
+
+architecture Behavioral of is_even is
+
+  signal y : STD_LOGIC_VECTOR (0 to 1);
+
+begin
+
+  y(0) <= x(0) xor x(1);
+  y(1) <= x(2) xor x(3);
+  o <= y(0) xor y(1);
+
+end Behavioral;
-- 
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