From feb78868167b4543c2ce87643f54761fea721605 Mon Sep 17 00:00:00 2001
From: Benjamin Chausse <benjamin@chausse.xyz>
Date: Sat, 3 May 2025 15:31:02 -0400
Subject: Follow instructions for parity check

---
 pb_APP_log_comb.srcs/sources_1/new/is_even.vhd     | 49 ----------------
 .../sources_1/new/parity_check.vhd                 | 66 ++++++++++++++++++++++
 2 files changed, 66 insertions(+), 49 deletions(-)
 delete mode 100644 pb_APP_log_comb.srcs/sources_1/new/is_even.vhd
 create mode 100644 pb_APP_log_comb.srcs/sources_1/new/parity_check.vhd

(limited to 'pb_APP_log_comb.srcs/sources_1')

diff --git a/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd b/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd
deleted file mode 100644
index 53eb4dc..0000000
--- a/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd
+++ /dev/null
@@ -1,49 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 05/03/2025 12:04:25 PM
--- Design Name:
--- Module Name: is_even - Behavioral
--- Project Name:
--- Target Devices:
--- Tool Versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity is_even is
-    Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
-           o : out STD_LOGIC);
-end is_even;
-
-architecture Behavioral of is_even is
-
-  signal y : STD_LOGIC_VECTOR (0 to 1);
-
-begin
-
-  y(0) <= x(0) xor x(1);
-  y(1) <= x(2) xor x(3);
-  o <= y(0) xor y(1);
-
-end Behavioral;
diff --git a/pb_APP_log_comb.srcs/sources_1/new/parity_check.vhd b/pb_APP_log_comb.srcs/sources_1/new/parity_check.vhd
new file mode 100644
index 0000000..50ffdfa
--- /dev/null
+++ b/pb_APP_log_comb.srcs/sources_1/new/parity_check.vhd
@@ -0,0 +1,66 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 05/03/2025 03:20:01 PM
+-- Design Name:
+-- Module Name: parity_check - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity parity_check is
+    Port ( ADCbin : in STD_LOGIC_VECTOR (3 downto 0);
+           S1 : in STD_LOGIC;
+           Parite : out STD_LOGIC);
+end parity_check;
+
+architecture Behavioral of parity_check is
+
+  signal Y : STD_LOGIC_VECTOR (2 downto 0);
+  signal PreFlip : STD_LOGIC;
+
+begin
+
+  Y(0) <= ADCbin(0) xor ADCbin(1);
+  Y(1) <= ADCbin(2) xor ADCbin(3);
+  Y(2) <= Y(0) xor Y(1);
+
+  flipCheck : process(Y, S1)
+  begin
+
+    case (S1) is
+      when '0' =>
+         Parite <= Y(2);
+      when '1' =>
+         Parite <= not Y(2);
+      when others =>
+         Parite <= '0';
+   end case;
+
+  end process;
+
+
+end Behavioral;
-- 
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