From 5c75255d353815db0b4efd02f60b70b89dc6d8ed Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Thu, 1 May 2025 09:15:48 -0400 Subject: more shit --- .../constrs_1/imports/contraintes/AppCombi_top.xdc | 102 ++++++++++++++ .../sim_1/imports/verif/AppCombi_top_tb.vhd | 154 +++++++++++++++++++++ 2 files changed, 256 insertions(+) create mode 100644 pb_APP_log_comb.srcs/constrs_1/imports/contraintes/AppCombi_top.xdc create mode 100644 pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd (limited to 'pb_APP_log_comb.srcs') diff --git a/pb_APP_log_comb.srcs/constrs_1/imports/contraintes/AppCombi_top.xdc b/pb_APP_log_comb.srcs/constrs_1/imports/contraintes/AppCombi_top.xdc new file mode 100644 index 0000000..0907a9b --- /dev/null +++ b/pb_APP_log_comb.srcs/constrs_1/imports/contraintes/AppCombi_top.xdc @@ -0,0 +1,102 @@ +## circuit_labo_adder_4b.xdc +## This file is a general .xdc for the Zybo Z7 Rev. B +## It is compatible with the Zybo Z7-20 and Zybo Z7-10 +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Adaptation circuit_labo_adder_4b +## D. Dalle, novembrere 2018 +## Simplification - retrait des lignes en double/triple +## M-A Tétrault, Janvier 2022 +## + +## Section préconfigurée - atelier, laboratoire et problématique + +##Clock signal +set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk +create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }]; + +##Switches (Circuit_Thermo_Bin, circuit_labo_adder_4b) +set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { i_sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0] +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { i_sw[1] }]; #IO_L24P_T3_34 Sch=sw[1] +set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { i_sw[2] }]; #IO_L4N_T0_34 Sch=sw[2] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { i_sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3] + +##Buttons (Circuit_Thermo_Bin, labo_adder4b) +set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { i_btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0] +set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { i_btn[1] }]; #IO_L24N_T3_34 Sch=btn[1] +set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { i_btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2] +set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { i_btn[3] }]; #IO_L7P_T1_34 Sch=btn[3] + + +##LEDs (Circuit_Thermo_Bin, labo_adder4b) +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { o_led[0] }]; #IO_L23P_T3_35 Sch=led[0] +set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_L23N_T3_35 Sch=led[1] +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { o_led[2] }]; #IO_0_35 Sch=led[2] +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { o_led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3] + +##RGB LED 6 (labo_adder4b a decider) +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { o_led6_r }]; #IO_L18P_T2_34 Sch=led6_r +##set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g +##set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b + + + +## Section préconfigurée - laboratoire et problématique +# Note: il faut retirer les "#" au début des lignes "set_property" +# pour activer ces liaisons physique + + +##Pmod Header JA (Circuit_Thermo_Bin, labo_adder4b: branchement: PmodSSD) +set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { o_SSD[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p # pmod haut +set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { o_SSD[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P # pmod haut +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { o_SSD[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P # pmod haut +set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { o_SSD[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P # pmod haut +set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { o_SSD[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N # pmod bas +set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { o_SSD[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N # pmod bas +set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { o_SSD[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N # pmod bas +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { o_SSD[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N # pmod bas + +##Pmod Header JC (Circuit_Thermo_Bin, circuit_labo_adder_4b: branchement : Pmod8LD) +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[0] }]; #IO_L10P_T1_34 Sch=jc_p[1] # pmod haut +set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[1] }]; #IO_L10N_T1_34 Sch=jc_n[1] # pmod haut +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[2] }]; #IO_L1P_T0_34 Sch=jc_p[2] # pmod haut +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[3] }]; #IO_L1N_T0_34 Sch=jc_n[2] # pmod haut +set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[4] }]; #IO_L8P_T1_34 Sch=jc_p[3] # pmod bas +set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[5] }]; #IO_L8N_T1_34 Sch=jc_n[3] # pmod bas +set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[6] }]; #IO_L2P_T0_34 Sch=jc_p[4] # pmod bas +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[7] }]; #IO_L2N_T0_34 Sch=jc_n[4] # pmod bas + + + +## Section partiellement préconfigurée - problématique +# Note: Vous devez renommer le nom du port pour correspondre à votre projet. +# Il faut également retirer les "#" au début des lignes "set_property" +# pour activer ces liaisons physique + +##Pmod Header JD (Circuit_Thermo_Bin) +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[0] }]; #IO_L5P_T0_34 Sch=jd_p[1] +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[1] }]; #IO_L5N_T0_34 Sch=jd_n[1] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[2] }]; #IO_L6P_T0_34 Sch=jd_p[2] +#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2] +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3] +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3] +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4] +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4] + +##Pmod Header JE (Circuit_Thermo_Bin) +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[8]}]; #IO_L4P_T0_34 Sch=je[1] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[9]}]; #IO_L18N_T2_34 Sch=je[2] +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[10] }]; #IO_25_35 Sch=je[3] +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { i_ADC_th[11] }]; #IO_L19P_T3_35 Sch=je[4] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { o_DEL2 }]; #IO_L3N_T0_DQS_34 Sch=je[7] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { o_DEL3 }]; #IO_L9N_T1_DQS_34 Sch=je[8] +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { i_S1 }]; #IO_L20P_T3_34 Sch=je[9] +#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { i_S2 }]; #IO_L7N_T1_34 Sch=je[10] + + + + + + diff --git a/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd new file mode 100644 index 0000000..0023bdc --- /dev/null +++ b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd @@ -0,0 +1,154 @@ +--------------------------------------------------------------------------------------------- +-- labo_adder4b_sol_tb.vhd +--------------------------------------------------------------------------------------------- +-- Université de Sherbrooke - Département de GEGI +-- Version : 3.0 +-- Nomenclature : GRAMS +-- Date Révision : 21 Avril 2020 +-- Auteur(s) : Réjean Fontaine, Daniel Dalle, Marc-André Tétrault +-- Technologies : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20) +-- peripheriques: carte Thermo12, Pmod8LD PmodSSD +-- +-- Outils : vivado 2019.1 64 bits +--------------------------------------------------------------------------------------------- +-- Description: +-- Banc d'essai pour circuit combinatoire Laboratoire logique combinatoire +-- Version avec entrées toutes combinatoires CIRCUIT COMPLET (TOP) +-- +-- Revision v1 12 novembre 2018, 3 décembre 2018 D. Dalle +-- Revision 30 Avril 2021, M-A Tetrault +-- +--------------------------------------------------------------------------------------------- +-- Notes : +-- L'entrée retenue (i_cin) est générée par l'interrupteur S1 de la carte Thermobin +-- +--------------------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +-- requis pour enoncés de type mem_valeurs_tests(to_integer( unsigned(table_valeurs_adr(9 downto 6) ))); +USE ieee.numeric_std.ALL; -- +use IEEE.STD_LOGIC_UNSIGNED.ALL; -- + + +entity AppCombi_top_tb is +-- Port ( ); +end AppCombi_top_tb; + +architecture Behavioral of AppCombi_top_tb is + +COMPONENT verif_show_affhex is +end COMPONENT; + +COMPONENT AppCombi_top + port ( + i_btn : in std_logic_vector (3 downto 0); + i_sw : in std_logic_vector (3 downto 0); + sysclk : in std_logic; + o_SSD : out std_logic_vector (7 downto 0); + o_led : out std_logic_vector (3 downto 0); + o_led6_r : out std_logic; + o_pmodled : out std_logic_vector (7 downto 0) + ); +end COMPONENT; + + signal clk_sim : STD_LOGIC := '0'; + signal pmodled_sim : STD_LOGIC_VECTOR (7 DOWNTO 0); + signal led_sim : STD_LOGIC_VECTOR (3 DOWNTO 0); + signal led6_r_sim : STD_LOGIC := '0'; + signal SSD_sim : STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000"; + signal sw_sim : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000"; + signal btn_sim : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000"; + signal cin_sim : STD_LOGIC := '0'; + signal vecteur_test_sim : STD_LOGIC_VECTOR (13 DOWNTO 0) := (others => '0'); + signal resultat_attendu : STD_LOGIC_VECTOR (4 DOWNTO 0) := "00000"; + + + constant sysclk_Period : time := 8 ns; + + + +---------------------------------------------------------------------------- +-- declaration d'un tableau pour soumettre un vecteur de test +---------------------------------------------------------------------------- + type table_valeurs_tests is array (integer range 0 to 63) of std_logic_vector(13 downto 0); + constant mem_valeurs_tests : table_valeurs_tests := + ( + -- vecteur de test è modifier selon les besoins + -- res op_a op_b cin + "00000" & "0000" & "0000" & '0', -- 0 + 0 + "00000" & "0000" & "0001" & '0', -- 0 + 1 + -- modifez et/ou ajoutez vos valeurs + + -- conserver la ligne ci-bas. + others => "00000" & "0000" & "0000" & '0' -- 0 + 0 + ); +---------------------------------------------------------------------------- + +begin + + +-- Pattes du FPGA Zybo-Z7 +uut: AppCombi_top + PORT MAP( + i_btn => btn_sim, + i_sw => sw_sim, + sysclk => clk_sim, + o_SSD => SSD_sim, + o_led => led_sim, + o_pmodled => pmodled_sim, + o_led6_r => led6_r_sim + ); + + + + -- Section banc de test + ---------------------------------------- + -- generation horloge + ---------------------------------------- + process + begin + clk_sim <= '1'; -- init + loop + wait for sysclk_Period/2; + clk_sim <= not clk_sim; -- invert clock value + end loop; + end process; + ---------------------------------------- + + ---------------------------------------- + -- test bench + tb : PROCESS + variable delai_sim : time := 50 ns; + variable table_valeurs_adr : integer range 0 to 63; + + BEGIN + -- Phase 1 + wait for delai_sim; + table_valeurs_adr := 0; + -- simuler une sequence de valeurs a l'entree + for index in 0 to mem_valeurs_tests'length-1 loop + vecteur_test_sim <= mem_valeurs_tests(table_valeurs_adr); + sw_sim <= vecteur_test_sim (8 downto 5); + btn_sim <= vecteur_test_sim (4 downto 1) ; + cin_sim <= vecteur_test_sim (0); + resultat_attendu <= vecteur_test_sim(13 downto 9); + wait for delai_sim; + --assert (resultat_attendu /= (probe_adder_result) ) report "Resultat pas celui prévu." severity warning; + table_valeurs_adr := table_valeurs_adr + 1; + if(table_valeurs_adr = 63) then + exit; + end if; + end loop; + + WAIT; -- will wait forever + END PROCESS; + +END Behavioral; -- cgit v1.2.3