From e2b14f5632ce509823eee95fb6641b568f08deca Mon Sep 17 00:00:00 2001 From: LYAM Date: Mon, 5 May 2025 13:41:17 -0400 Subject: Added DEls and buttons to it --- .../constrs_1/imports/contraintes/AppCombi_top.xdc | 8 +++--- .../sources_1/imports/src/AppCombi_top.vhd | 29 ++++++++++++++++++++-- pb_APP_log_comb.srcs/sources_1/new/fct_2_3_tb.vhd | 8 +++--- 3 files changed, 35 insertions(+), 10 deletions(-) (limited to 'pb_APP_log_comb.srcs') diff --git a/pb_APP_log_comb.srcs/constrs_1/imports/contraintes/AppCombi_top.xdc b/pb_APP_log_comb.srcs/constrs_1/imports/contraintes/AppCombi_top.xdc index d600b2b..5147819 100644 --- a/pb_APP_log_comb.srcs/constrs_1/imports/contraintes/AppCombi_top.xdc +++ b/pb_APP_log_comb.srcs/constrs_1/imports/contraintes/AppCombi_top.xdc @@ -90,10 +90,10 @@ set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { ADCth[ set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { ADCth[9]}]; #IO_L18N_T2_34 Sch=je[2] set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { ADCth[10] }]; #IO_25_35 Sch=je[3] set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ADCth[11] }]; #IO_L19P_T3_35 Sch=je[4] -#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { o_DEL2 }]; #IO_L3N_T0_DQS_34 Sch=je[7] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { o_DEL3 }]; #IO_L9N_T1_DQS_34 Sch=je[8] -#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { i_S1 }]; #IO_L20P_T3_34 Sch=je[9] -#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { i_S2 }]; #IO_L7N_T1_34 Sch=je[10] +set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { DEL2 }]; #IO_L3N_T0_DQS_34 Sch=je[7] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { DEL3 }]; #IO_L9N_T1_DQS_34 Sch=je[8] +set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { button_s1 }]; #IO_L20P_T3_34 Sch=je[9] +set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { button_s2 }]; #IO_L7N_T1_34 Sch=je[10] diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd index c645919..d2043c4 100644 --- a/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd +++ b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd @@ -33,7 +33,11 @@ entity AppCombi_top is port ( o_led : out std_logic_vector (3 downto 0); -- vers DELs de la carte Zybo o_led6_r : out std_logic; -- vers DEL rouge de la carte Zybo o_pmodled : out std_logic_vector (7 downto 0); -- vers connecteur pmod 8 DELs - ADCth : in std_logic_vector (11 downto 0) -- Connecteur ADCth thermometrique + ADCth : in std_logic_vector (11 downto 0); -- Connecteur ADCth thermometrique + DEL1 : out std_logic; -- Carte thermometrique + DEL2 : out std_logic; -- Carte thermometrique + button_s1 : in std_logic; -- Carte thermometrique + button_s2 : in std_logic -- Carte thermometrique ); end AppCombi_top; @@ -59,6 +63,14 @@ architecture BEHAVIORAL of AppCombi_top is signal error : std_logic := '0'; -- PMOD signal A2_3 : std_logic_vector (2 downto 0) := "000"; + -- + signal parite_out : std_logic := '0'; + + component parity_check is Port ( + ADCbin : in STD_LOGIC_VECTOR (3 downto 0); + S1 : in STD_LOGIC; + Parite : out STD_LOGIC); + end component; component Fct_2_3 is Port ( ADCbin : in STD_LOGIC_VECTOR (3 downto 0); @@ -142,6 +154,19 @@ begin bus_out => o_pmodled ); + ---------------------------------------- + -- Parite + ---------------------------------------- + parity : parity_check port map ( + ADCbin => ADCbin, + S1 => button_s1, + Parite => parite_out + ); + + DEL2 <= parite_out; + o_led(0) <= parite_out; + + adder4 : Add4Bits port map ( A => d_opa, B => d_opb, @@ -160,7 +185,7 @@ begin d_AFF1 <= ADCth(6 downto 2); --'0' & '0' & '0' & '0' & d_Cout; -- La retenue de sortie affichée sur PmodSSD(1) (0 ou 1) o_led6_r <= d_Cout; -- La led couleur représente aussi la retenue en sortie Cout --o_pmodled <= d_opa & d_opb; -- Les opérandes d'entrés reproduits combinés sur Pmod8LD - o_led (3 downto 0) <= '0' & '0' & '0' & d_S_1Hz; -- La LED0 sur la carte représente la retenue d'entrée + --o_led (3 downto 0) <= '0' & '0' & '0' & d_S_1Hz; -- La LED0 sur la carte représente la retenue d'entrée end BEHAVIORAL; diff --git a/pb_APP_log_comb.srcs/sources_1/new/fct_2_3_tb.vhd b/pb_APP_log_comb.srcs/sources_1/new/fct_2_3_tb.vhd index 0f74165..2d89a59 100644 --- a/pb_APP_log_comb.srcs/sources_1/new/fct_2_3_tb.vhd +++ b/pb_APP_log_comb.srcs/sources_1/new/fct_2_3_tb.vhd @@ -67,10 +67,10 @@ architecture Behavioral of fct_2_3_tb is "001" & "0011", "010" & "0100", "010" & "0101", - "011" & "0110", - "011" & "0111", - "101" & "1000", - "101" & "1001", + "011" & "0110", -- 0011, 0000 + "011" & "0111", -- 0011, 0000 + "101" & "1000", -- 0100, 0001 + "101" & "1001", -- 0100, 0001 "110" & "1010", "110" & "1011", "111" & "1100", -- 12 -- cgit v1.2.3