From 8fd60d09f6f0b63c1b555efbda1242fe9fa39bcc Mon Sep 17 00:00:00 2001
From: Benjamin Chausse <benjamin@chausse.xyz>
Date: Tue, 6 May 2025 12:40:25 -0400
Subject: Annex work

---
 rapport/annexe.tex | 37 +++++++++++++++++++++++++++++++++++--
 1 file changed, 35 insertions(+), 2 deletions(-)

(limited to 'rapport/annexe.tex')

diff --git a/rapport/annexe.tex b/rapport/annexe.tex
index f15f688..0c43f81 100644
--- a/rapport/annexe.tex
+++ b/rapport/annexe.tex
@@ -1,6 +1,7 @@
 \newpage
 \appendix
 \section{Code VHDL}
+\todo{Finish this this}
 
 \begin{figure}[H]
   \tiny
@@ -11,8 +12,40 @@
 \caption{Module Thermo2bin}
 \end{figure}
 
-\section{Simulations}
+\begin{figure}[H]
+  \tiny
+\centering
+\begin{varwidth}{\linewidth}
+  \input{assets/code/add4bits.tex}
+\end{varwidth}
+\caption{Module Add4Bits}
+\end{figure}
 
-\section{Tables de Vérité et Karnaugh}
+\begin{figure}[H]
+  \tiny
+\centering
+\begin{varwidth}{\linewidth}
+  \input{assets/code/add1bita.tex}
+\end{varwidth}
+\caption{Module Add1BitA}
+\end{figure}
+
+\begin{figure}[H]
+  \tiny
+\centering
+\begin{varwidth}{\linewidth}
+  \input{assets/code/add1bitb.tex}
+\end{varwidth}
+\caption{Module Add1BitB}
+\end{figure}
+
+\section{Schémas}
 
+\todo{Schéma bloc}\\
+\todo{Simulations}
+
+
+\section{Tables de Vérité et Karnaugh}
 
+\todo{Verite}\\
+\todo{Karnaugh}
-- 
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