From 3d81cfe9c1028ae989f580e42aad0414081b5e7c Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Sun, 18 May 2025 14:07:21 -0400 Subject: Batman --- .../sources_1/bd/design_1/hdl/design_1_wrapper.vhd | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 pb_logique_seq.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd (limited to 'pb_logique_seq.gen/sources_1/bd/design_1/hdl') diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd new file mode 100644 index 0000000..792a63b --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd @@ -0,0 +1,58 @@ +--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +--Date : Tue Jan 16 11:48:36 2024 +--Host : gegi-3014-bmwin running 64-bit major release (build 9200) +--Command : generate_target design_1_wrapper.bd +--Design : design_1_wrapper +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity design_1_wrapper is + port ( + JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 ); + clk_100MHz : in STD_LOGIC; + i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 ); + i_lrc : in STD_LOGIC; + i_recdat : in STD_LOGIC; + i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 ); + o_param : out STD_LOGIC_VECTOR ( 7 downto 0 ); + o_pbdat : out STD_LOGIC_VECTOR ( 0 to 0 ); + o_sel_fct : out STD_LOGIC_VECTOR ( 1 downto 0 ); + o_sel_par : out STD_LOGIC_VECTOR ( 1 downto 0 ) + ); +end design_1_wrapper; + +architecture STRUCTURE of design_1_wrapper is + component design_1 is + port ( + i_recdat : in STD_LOGIC; + i_lrc : in STD_LOGIC; + i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 ); + i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 ); + clk_100MHz : in STD_LOGIC; + o_pbdat : out STD_LOGIC_VECTOR ( 0 to 0 ); + JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 ); + o_param : out STD_LOGIC_VECTOR ( 7 downto 0 ); + o_sel_par : out STD_LOGIC_VECTOR ( 1 downto 0 ); + o_sel_fct : out STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + end component design_1; +begin +design_1_i: component design_1 + port map ( + JPmod(7 downto 0) => JPmod(7 downto 0), + clk_100MHz => clk_100MHz, + i_btn(3 downto 0) => i_btn(3 downto 0), + i_lrc => i_lrc, + i_recdat => i_recdat, + i_sw(3 downto 0) => i_sw(3 downto 0), + o_param(7 downto 0) => o_param(7 downto 0), + o_pbdat(0) => o_pbdat(0), + o_sel_fct(1 downto 0) => o_sel_fct(1 downto 0), + o_sel_par(1 downto 0) => o_sel_par(1 downto 0) + ); +end STRUCTURE; -- cgit v1.2.3