From 3d81cfe9c1028ae989f580e42aad0414081b5e7c Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Sun, 18 May 2025 14:07:21 -0400 Subject: Batman --- .../design_1_M10_conversion_affichage_0.xml | 235 + .../design_1_M2_fonction_distortion_dure1_0.xml | 75 + .../design_1_M3_fonction_distorsion_dure2_0.xml | 72 + .../design_1_M4_fonction3_0.xml | 60 + .../design_1_M5_parametre_1_0.xml | 137 + .../design_1_M6_parametre_2_0.xml | 137 + .../design_1_M7_parametre_3_0.xml | 137 + .../design_1_M8_commande_0.xml | 282 ++ .../design_1_MEF_decodeur_i2s_0.xml | 218 + .../design_1_Multiplexeur_choix_fonction_0.xml | 136 + .../design_1_Multiplexeur_choix_parametre_0.xml | 139 + .../design_1_affhexPmodSSD_v3_0_0.xml | 385 ++ .../sim/design_1_affhexPmodSSD_v3_0_0.vhd | 101 + .../synth/design_1_affhexPmodSSD_v3_0_0.vhd | 107 + .../design_1_calcul_param_1_0_0.dcp | Bin 0 -> 6371 bytes .../design_1_calcul_param_1_0_0.xml | 291 ++ .../design_1_calcul_param_1_0_0_sim_netlist.v | 128 + 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design_1_M10_conversion_affichage_0 + 1.0 + + + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + clk + + in + + + STD_LOGIC + dummy_view + + + + + + reset + + in + + + STD_LOGIC + dummy_view + + + + + + DA + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + i_btn + + in + + 3 + 0 + + + + STD_LOGIC_vector + dummy_view + + + + + + JPmod + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + + + const_CLK_Hz + Const Clk Hz + 100000000 + + + + xilinx.com:module_ref:affhexPmodSSD_v3:1.0 + + + const_CLK_Hz + Const Clk Hz + 100000000 + + + Component_Name + design_1_M10_conversion_affichage_0 + + + + + affhexPmodSSD_v3_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M2_fonction_distortion_dure1_0/design_1_M2_fonction_distortion_dure1_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M2_fonction_distortion_dure1_0/design_1_M2_fonction_distortion_dure1_0.xml new file mode 100644 index 0000000..d92a60e --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M2_fonction_distortion_dure1_0/design_1_M2_fonction_distortion_dure1_0.xml @@ -0,0 +1,75 @@ + + + xilinx.com + customized_ip + design_1_M2_fonction_distortion_dure1_0 + 1.0 + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_ech_fct + + out + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + c_ech_u24_max + C Ech U24 Max + 0x7FFFFF + + + + xilinx.com:module_ref:sig_fct_sat_dure:1.0 + + + c_ech_u24_max + C Ech U24 Max + 0x7FFFFF + + + Component_Name + design_1_M2_fonction_distortion_dure1_0 + + + + + sig_fct_sat_dure_v1_0 + module_ref + 1 + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M3_fonction_distorsion_dure2_0/design_1_M3_fonction_distorsion_dure2_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M3_fonction_distorsion_dure2_0/design_1_M3_fonction_distorsion_dure2_0.xml new file mode 100644 index 0000000..b2cce85 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M3_fonction_distorsion_dure2_0/design_1_M3_fonction_distorsion_dure2_0.xml @@ -0,0 +1,72 @@ + + + xilinx.com + customized_ip + design_1_M3_fonction_distorsion_dure2_0 + 1.0 + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_ech_fct + + out + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + c_ech_u24_max + C Ech U24 Max + 0x1FFFFF + + + + xilinx.com:module_ref:sig_fct_sat_dure:1.0 + + + c_ech_u24_max + C Ech U24 Max + 0x1FFFFF + + + Component_Name + design_1_M3_fonction_distorsion_dure2_0 + + + + + sig_fct_sat_dure_v1_0 + module_ref + 1 + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M4_fonction3_0/design_1_M4_fonction3_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M4_fonction3_0/design_1_M4_fonction3_0.xml new file mode 100644 index 0000000..13c57fb --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M4_fonction3_0/design_1_M4_fonction3_0.xml @@ -0,0 +1,60 @@ + + + xilinx.com + customized_ip + design_1_M4_fonction3_0 + 1.0 + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_ech_fct + + out + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + + xilinx.com:module_ref:sig_fct_3:1.0 + + + Component_Name + design_1_M4_fonction3_0 + + + + + sig_fct_3_v1_0 + module_ref + 1 + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M5_parametre_1_0/design_1_M5_parametre_1_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M5_parametre_1_0/design_1_M5_parametre_1_0.xml new file mode 100644 index 0000000..5ad0698 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M5_parametre_1_0/design_1_M5_parametre_1_0.xml @@ -0,0 +1,137 @@ + + + xilinx.com + customized_ip + design_1_M5_parametre_1_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + i_bclk + + in + + + std_logic + dummy_view + + + + + + i_reset + + in + + + std_logic + dummy_view + + + + + + i_en + + in + + + std_logic + dummy_view + + + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_param + + out + + 7 + 0 + + + + std_logic_vector + dummy_view + + + + + + + xilinx.com:module_ref:calcul_param_1:1.0 + + + Component_Name + design_1_M5_parametre_1_0 + + + + + calcul_param_1_v1_0 + module_ref + 1 + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M6_parametre_2_0/design_1_M6_parametre_2_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M6_parametre_2_0/design_1_M6_parametre_2_0.xml new file mode 100644 index 0000000..e894217 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M6_parametre_2_0/design_1_M6_parametre_2_0.xml @@ -0,0 +1,137 @@ + + + xilinx.com + customized_ip + design_1_M6_parametre_2_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + i_bclk + + in + + + std_logic + dummy_view + + + + + + i_reset + + in + + + std_logic + dummy_view + + + + + + i_en + + in + + + std_logic + dummy_view + + + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_param + + out + + 7 + 0 + + + + std_logic_vector + dummy_view + + + + + + + xilinx.com:module_ref:calcul_param_2:1.0 + + + Component_Name + design_1_M6_parametre_2_0 + + + + + calcul_param_2_v1_0 + module_ref + 1 + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M7_parametre_3_0/design_1_M7_parametre_3_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M7_parametre_3_0/design_1_M7_parametre_3_0.xml new file mode 100644 index 0000000..f6bafd7 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M7_parametre_3_0/design_1_M7_parametre_3_0.xml @@ -0,0 +1,137 @@ + + + xilinx.com + customized_ip + design_1_M7_parametre_3_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + i_bclk + + in + + + std_logic + dummy_view + + + + + + i_reset + + in + + + std_logic + dummy_view + + + + + + i_en + + in + + + std_logic + dummy_view + + + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_param + + out + + 7 + 0 + + + + std_logic_vector + dummy_view + + + + + + + xilinx.com:module_ref:calcul_param_3:1.0 + + + Component_Name + design_1_M7_parametre_3_0 + + + + + calcul_param_3_v1_0 + module_ref + 1 + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M8_commande_0/design_1_M8_commande_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M8_commande_0/design_1_M8_commande_0.xml new file mode 100644 index 0000000..475f524 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M8_commande_0/design_1_M8_commande_0.xml @@ -0,0 +1,282 @@ + + + xilinx.com + customized_ip + design_1_M8_commande_0 + 1.0 + + + o_reset + + + + + + + RST + + + o_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + clk + + + + + + + CLK + + + clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + clk + + in + + + std_logic + dummy_view + + + + + + o_reset + + out + + + std_logic + dummy_view + + + + + + i_btn + + in + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + + + i_sw + + in + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_btn_cd + + out + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_selection_fct + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_selection_par + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + nbtn + Nbtn + 4 + + + mode_simulation + Mode Simulation + "0" + + + + xilinx.com:module_ref:module_commande:1.0 + + + nbtn + Nbtn + 4 + + + mode_simulation + Mode Simulation + "0" + + + Component_Name + design_1_M8_commande_0 + + + + + module_commande_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_MEF_decodeur_i2s_0/design_1_MEF_decodeur_i2s_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_MEF_decodeur_i2s_0/design_1_MEF_decodeur_i2s_0.xml new file mode 100644 index 0000000..8354d27 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_MEF_decodeur_i2s_0/design_1_MEF_decodeur_i2s_0.xml @@ -0,0 +1,218 @@ + + + xilinx.com + customized_ip + design_1_MEF_decodeur_i2s_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + o_cpt_bit_reset + + + + + + + RST + + + o_cpt_bit_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + i_bclk + + in + + + std_logic + dummy_view + + + + + + i_reset + + in + + + std_logic + dummy_view + + + + + + i_lrc + + in + + + std_logic + dummy_view + + + + + + i_cpt_bits + + in + + 6 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_bit_enable + + out + + + std_logic + dummy_view + + + + + + o_load_left + + out + + + std_logic + dummy_view + + + + + + o_load_right + + out + + + std_logic + dummy_view + + + + + + o_str_dat + + out + + + std_logic + dummy_view + + + + + + o_cpt_bit_reset + + out + + + std_logic + dummy_view + + + + + + + xilinx.com:module_ref:mef_decod_i2s_v1b:1.0 + + + Component_Name + design_1_MEF_decodeur_i2s_0 + + + + + mef_decod_i2s_v1b_v1_0 + module_ref + 1 + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_fonction_0/design_1_Multiplexeur_choix_fonction_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_fonction_0/design_1_Multiplexeur_choix_fonction_0.xml new file mode 100644 index 0000000..8575b0b --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_fonction_0/design_1_Multiplexeur_choix_fonction_0.xml @@ -0,0 +1,136 @@ + + + xilinx.com + customized_ip + design_1_Multiplexeur_choix_fonction_0 + 1.0 + + + + input0 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + input1 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + input2 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + input3 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + sel + + in + + 1 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + output0 + + out + + 23 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + + + input_length + Input Length + 24 + + + + xilinx.com:module_ref:mux4:1.0 + + + input_length + Input Length + 24 + + + Component_Name + design_1_Multiplexeur_choix_fonction_0 + + + + + mux4_v1_0 + module_ref + 1 + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_parametre_0/design_1_Multiplexeur_choix_parametre_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_parametre_0/design_1_Multiplexeur_choix_parametre_0.xml new file mode 100644 index 0000000..8da7108 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_parametre_0/design_1_Multiplexeur_choix_parametre_0.xml @@ -0,0 +1,139 @@ + + + xilinx.com + customized_ip + design_1_Multiplexeur_choix_parametre_0 + 1.0 + + + + input0 + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + input1 + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + input2 + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + input3 + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + sel + + in + + 1 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + output0 + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + + + input_length + Input Length + 8 + + + + xilinx.com:module_ref:mux4:1.0 + + + input_length + Input Length + 8 + + + Component_Name + design_1_Multiplexeur_choix_parametre_0 + + + + + mux4_v1_0 + module_ref + 1 + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/design_1_affhexPmodSSD_v3_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/design_1_affhexPmodSSD_v3_0_0.xml new file mode 100644 index 0000000..515b225 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/design_1_affhexPmodSSD_v3_0_0.xml @@ -0,0 +1,385 @@ + + + xilinx.com + customized_ip + design_1_affhexPmodSSD_v3_0_0 + 1.0 + + + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + affhexPmodSSD_v3 + + + outputProductCRC + 9:a72dafd7 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_affhexPmodSSD_v3_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:a72dafd7 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + affhexPmodSSD_v3 + + + outputProductCRC + 9:94feae58 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:94feae58 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_affhexPmodSSD_v3_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:94feae58 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:94feae58 + + + + + + + clk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reset + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + DA + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_btn + + in + + 3 + 0 + + + + STD_LOGIC_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + JPmod + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + const_CLK_Hz + Const Clk Hz + 100000000 + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_affhexPmodSSD_v3_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_affhexPmodSSD_v3_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_affhexPmodSSD_v3_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_affhexPmodSSD_v3_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_affhexPmodSSD_v3_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_affhexPmodSSD_v3_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_affhexPmodSSD_v3_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:affhexPmodSSD_v3:1.0 + + + const_CLK_Hz + Const Clk Hz + 100000000 + + + Component_Name + design_1_affhexPmodSSD_v3_0_0 + + + + + affhexPmodSSD_v3_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd new file mode 100644 index 0000000..0c61365 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd @@ -0,0 +1,101 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:affhexPmodSSD_v3:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_affhexPmodSSD_v3_0_0 IS + PORT ( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END design_1_affhexPmodSSD_v3_0_0; + +ARCHITECTURE design_1_affhexPmodSSD_v3_0_0_arch OF design_1_affhexPmodSSD_v3_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT affhexPmodSSD_v3 IS + GENERIC ( + const_CLK_Hz : INTEGER + ); + PORT ( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT affhexPmodSSD_v3; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; +BEGIN + U0 : affhexPmodSSD_v3 + GENERIC MAP ( + const_CLK_Hz => 100000000 + ) + PORT MAP ( + clk => clk, + reset => reset, + DA => DA, + i_btn => i_btn, + JPmod => JPmod + ); +END design_1_affhexPmodSSD_v3_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/synth/design_1_affhexPmodSSD_v3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/synth/design_1_affhexPmodSSD_v3_0_0.vhd new file mode 100644 index 0000000..863e38e --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/synth/design_1_affhexPmodSSD_v3_0_0.vhd @@ -0,0 +1,107 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:affhexPmodSSD_v3:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_affhexPmodSSD_v3_0_0 IS + PORT ( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END design_1_affhexPmodSSD_v3_0_0; + +ARCHITECTURE design_1_affhexPmodSSD_v3_0_0_arch OF design_1_affhexPmodSSD_v3_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT affhexPmodSSD_v3 IS + GENERIC ( + const_CLK_Hz : INTEGER + ); + PORT ( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT affhexPmodSSD_v3; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "affhexPmodSSD_v3,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_affhexPmodSSD_v3_0_0_arch : ARCHITECTURE IS "design_1_affhexPmodSSD_v3_0_0,affhexPmodSSD_v3,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "design_1_affhexPmodSSD_v3_0_0,affhexPmodSSD_v3,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=affhexPmodSSD_v3,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,const_CLK_Hz=100000000}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; +BEGIN + U0 : affhexPmodSSD_v3 + GENERIC MAP ( + const_CLK_Hz => 100000000 + ) + PORT MAP ( + clk => clk, + reset => reset, + DA => DA, + i_btn => i_btn, + JPmod => JPmod + ); +END design_1_affhexPmodSSD_v3_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.dcp new file mode 100644 index 0000000..35abe7c Binary files /dev/null and b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.dcp differ diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.xml new file mode 100644 index 0000000..aa175bb --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.xml @@ -0,0 +1,291 @@ + + + xilinx.com + customized_ip + design_1_calcul_param_1_0_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + calcul_param_1 + + + outputProductCRC + 9:51a74f2b + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_calcul_param_1_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:51a74f2b + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + calcul_param_1 + + + outputProductCRC + 9:f071fa08 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:f071fa08 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_calcul_param_1_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:f071fa08 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Tue Jan 16 17:00:21 UTC 2024 + + + outputProductCRC + 9:f071fa08 + + + + + + + i_bclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_param + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_calcul_param_1_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_calcul_param_1_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_calcul_param_1_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_calcul_param_1_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_calcul_param_1_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_calcul_param_1_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_calcul_param_1_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:calcul_param_1:1.0 + + + Component_Name + design_1_calcul_param_1_0_0 + + + + + calcul_param_1_v1_0 + module_ref + 1 + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_sim_netlist.v new file mode 100644 index 0000000..02b702d --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_sim_netlist.v @@ -0,0 +1,128 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 12:00:21 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_sim_netlist.v +// Design : design_1_calcul_param_1_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "design_1_calcul_param_1_0_0,calcul_param_1,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) +(* x_core_info = "calcul_param_1,Vivado 2020.2" *) +(* NotValidForBitStream *) +module design_1_calcul_param_1_0_0 + (i_bclk, + i_reset, + i_en, + i_ech, + o_param); + input i_bclk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 i_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input i_reset; + input i_en; + input [23:0]i_ech; + output [7:0]o_param; + + wire \ ; + wire \ ; + + assign o_param[7] = \ ; + assign o_param[6] = \ ; + assign o_param[5] = \ ; + assign o_param[4] = \ ; + assign o_param[3] = \ ; + assign o_param[2] = \ ; + assign o_param[1] = \ ; + assign o_param[0] = \ ; + GND GND + (.G(\ )); + VCC VCC + (.P(\ )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_stub.v new file mode 100644 index 0000000..136308e --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_stub.v @@ -0,0 +1,24 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 12:00:21 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_stub.v +// Design : design_1_calcul_param_1_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "calcul_param_1,Vivado 2020.2" *) +module design_1_calcul_param_1_0_0(i_bclk, i_reset, i_en, i_ech, o_param) +/* synthesis syn_black_box black_box_pad_pin="i_bclk,i_reset,i_en,i_ech[23:0],o_param[7:0]" */; + input i_bclk; + input i_reset; + input i_en; + input [23:0]i_ech; + output [7:0]o_param; +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd new file mode 100644 index 0000000..b90cd0b --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd @@ -0,0 +1,93 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:calcul_param_1:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_calcul_param_1_0_0 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END design_1_calcul_param_1_0_0; + +ARCHITECTURE design_1_calcul_param_1_0_0_arch OF design_1_calcul_param_1_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT calcul_param_1 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT calcul_param_1; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; +BEGIN + U0 : calcul_param_1 + PORT MAP ( + i_bclk => i_bclk, + i_reset => i_reset, + i_en => i_en, + i_ech => i_ech, + o_param => o_param + ); +END design_1_calcul_param_1_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/synth/design_1_calcul_param_1_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/synth/design_1_calcul_param_1_0_0.vhd new file mode 100644 index 0000000..12f30ce --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/synth/design_1_calcul_param_1_0_0.vhd @@ -0,0 +1,99 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:calcul_param_1:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_calcul_param_1_0_0 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END design_1_calcul_param_1_0_0; + +ARCHITECTURE design_1_calcul_param_1_0_0_arch OF design_1_calcul_param_1_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT calcul_param_1 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT calcul_param_1; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "calcul_param_1,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_calcul_param_1_0_0_arch : ARCHITECTURE IS "design_1_calcul_param_1_0_0,calcul_param_1,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "design_1_calcul_param_1_0_0,calcul_param_1,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=calcul_param_1,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; +BEGIN + U0 : calcul_param_1 + PORT MAP ( + i_bclk => i_bclk, + i_reset => i_reset, + i_en => i_en, + i_ech => i_ech, + o_param => o_param + ); +END design_1_calcul_param_1_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.dcp new file mode 100644 index 0000000..fc20102 Binary files /dev/null and b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.dcp differ diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.xml new file mode 100644 index 0000000..9c943ae --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.xml @@ -0,0 +1,291 @@ + + + xilinx.com + customized_ip + design_1_calcul_param_2_0_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + calcul_param_2 + + + outputProductCRC + 9:aa79c05c + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_calcul_param_2_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:aa79c05c + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + calcul_param_2 + + + outputProductCRC + 9:7d5ec9e3 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:7d5ec9e3 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_calcul_param_2_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:7d5ec9e3 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Tue Jan 16 17:00:21 UTC 2024 + + + outputProductCRC + 9:7d5ec9e3 + + + + + + + i_bclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_param + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_calcul_param_2_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_calcul_param_2_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_calcul_param_2_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_calcul_param_2_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_calcul_param_2_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_calcul_param_2_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_calcul_param_2_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:calcul_param_2:1.0 + + + Component_Name + design_1_calcul_param_2_0_0 + + + + + calcul_param_2_v1_0 + module_ref + 1 + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_sim_netlist.v new file mode 100644 index 0000000..60d05dd --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_sim_netlist.v @@ -0,0 +1,128 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 12:00:21 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_sim_netlist.v +// Design : design_1_calcul_param_2_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "design_1_calcul_param_2_0_0,calcul_param_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) +(* x_core_info = "calcul_param_2,Vivado 2020.2" *) +(* NotValidForBitStream *) +module design_1_calcul_param_2_0_0 + (i_bclk, + i_reset, + i_en, + i_ech, + o_param); + input i_bclk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 i_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input i_reset; + input i_en; + input [23:0]i_ech; + output [7:0]o_param; + + wire \ ; + wire \ ; + + assign o_param[7] = \ ; + assign o_param[6] = \ ; + assign o_param[5] = \ ; + assign o_param[4] = \ ; + assign o_param[3] = \ ; + assign o_param[2] = \ ; + assign o_param[1] = \ ; + assign o_param[0] = \ ; + GND GND + (.G(\ )); + VCC VCC + (.P(\ )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_stub.v new file mode 100644 index 0000000..f6f6e3e --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_stub.v @@ -0,0 +1,24 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 12:00:21 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_stub.v +// Design : design_1_calcul_param_2_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "calcul_param_2,Vivado 2020.2" *) +module design_1_calcul_param_2_0_0(i_bclk, i_reset, i_en, i_ech, o_param) +/* synthesis syn_black_box black_box_pad_pin="i_bclk,i_reset,i_en,i_ech[23:0],o_param[7:0]" */; + input i_bclk; + input i_reset; + input i_en; + input [23:0]i_ech; + output [7:0]o_param; +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd new file mode 100644 index 0000000..aeda442 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd @@ -0,0 +1,93 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:calcul_param_2:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_calcul_param_2_0_0 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END design_1_calcul_param_2_0_0; + +ARCHITECTURE design_1_calcul_param_2_0_0_arch OF design_1_calcul_param_2_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT calcul_param_2 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT calcul_param_2; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; +BEGIN + U0 : calcul_param_2 + PORT MAP ( + i_bclk => i_bclk, + i_reset => i_reset, + i_en => i_en, + i_ech => i_ech, + o_param => o_param + ); +END design_1_calcul_param_2_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/synth/design_1_calcul_param_2_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/synth/design_1_calcul_param_2_0_0.vhd new file mode 100644 index 0000000..6a99f75 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/synth/design_1_calcul_param_2_0_0.vhd @@ -0,0 +1,99 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:calcul_param_2:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_calcul_param_2_0_0 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END design_1_calcul_param_2_0_0; + +ARCHITECTURE design_1_calcul_param_2_0_0_arch OF design_1_calcul_param_2_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT calcul_param_2 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT calcul_param_2; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "calcul_param_2,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_calcul_param_2_0_0_arch : ARCHITECTURE IS "design_1_calcul_param_2_0_0,calcul_param_2,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "design_1_calcul_param_2_0_0,calcul_param_2,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=calcul_param_2,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; +BEGIN + U0 : calcul_param_2 + PORT MAP ( + i_bclk => i_bclk, + i_reset => i_reset, + i_en => i_en, + i_ech => i_ech, + o_param => o_param + ); +END design_1_calcul_param_2_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/design_1_calcul_param_3_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/design_1_calcul_param_3_0_0.xml new file mode 100644 index 0000000..96be4aa --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/design_1_calcul_param_3_0_0.xml @@ -0,0 +1,287 @@ + + + xilinx.com + customized_ip + design_1_calcul_param_3_0_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + calcul_param_3 + + + outputProductCRC + 9:fccc4571 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_calcul_param_3_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:fccc4571 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + calcul_param_3 + + + outputProductCRC + 9:b094da85 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:b094da85 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_calcul_param_3_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:b094da85 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:b094da85 + + + + + + + i_bclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_param + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_calcul_param_3_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_calcul_param_3_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_calcul_param_3_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_calcul_param_3_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_calcul_param_3_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_calcul_param_3_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_calcul_param_3_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:calcul_param_3:1.0 + + + Component_Name + design_1_calcul_param_3_0_0 + + + + + calcul_param_3_v1_0 + module_ref + 1 + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd new file mode 100644 index 0000000..bc012a0 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd @@ -0,0 +1,93 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:calcul_param_3:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_calcul_param_3_0_0 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END design_1_calcul_param_3_0_0; + +ARCHITECTURE design_1_calcul_param_3_0_0_arch OF design_1_calcul_param_3_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT calcul_param_3 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT calcul_param_3; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; +BEGIN + U0 : calcul_param_3 + PORT MAP ( + i_bclk => i_bclk, + i_reset => i_reset, + i_en => i_en, + i_ech => i_ech, + o_param => o_param + ); +END design_1_calcul_param_3_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/synth/design_1_calcul_param_3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/synth/design_1_calcul_param_3_0_0.vhd new file mode 100644 index 0000000..93f83b7 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/synth/design_1_calcul_param_3_0_0.vhd @@ -0,0 +1,99 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:calcul_param_3:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_calcul_param_3_0_0 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END design_1_calcul_param_3_0_0; + +ARCHITECTURE design_1_calcul_param_3_0_0_arch OF design_1_calcul_param_3_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT calcul_param_3 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT calcul_param_3; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "calcul_param_3,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_calcul_param_3_0_0_arch : ARCHITECTURE IS "design_1_calcul_param_3_0_0,calcul_param_3,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "design_1_calcul_param_3_0_0,calcul_param_3,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=calcul_param_3,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; +BEGIN + U0 : calcul_param_3 + PORT MAP ( + i_bclk => i_bclk, + i_reset => i_reset, + i_en => i_en, + i_ech => i_ech, + o_param => o_param + ); +END design_1_calcul_param_3_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_7bits_0/design_1_compteur_7bits_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_7bits_0/design_1_compteur_7bits_0.xml new file mode 100644 index 0000000..2a80f63 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_7bits_0/design_1_compteur_7bits_0.xml @@ -0,0 +1,216 @@ + + + xilinx.com + customized_ip + design_1_compteur_7bits_0 + 1.0 + + + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + clk + + in + + + std_logic + dummy_view + + + + + + i_en + + in + + + std_logic + dummy_view + + + + + + reset + + in + + + std_logic + dummy_view + + + + + + o_val_cpt + + out + + 6 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + nbits + Nbits + 7 + + + + xilinx.com:module_ref:compteur_nbits:1.0 + + + nbits + Nbits + 7 + + + Component_Name + design_1_compteur_7bits_0 + + + + + compteur_nbits_v1_0 + module_ref + 1 + + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/design_1_compteur_nbits_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/design_1_compteur_nbits_0_0.xml new file mode 100644 index 0000000..914dae7 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/design_1_compteur_nbits_0_0.xml @@ -0,0 +1,365 @@ + + + xilinx.com + customized_ip + design_1_compteur_nbits_0_0 + 1.0 + + + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + compteur_nbits + + + outputProductCRC + 9:f6adf5ff + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_compteur_nbits_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:f6adf5ff + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + compteur_nbits + + + outputProductCRC + 9:8075707d + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:8075707d + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_compteur_nbits_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:8075707d + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:8075707d + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_val_cpt + + out + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + nbits + Nbits + 7 + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_compteur_nbits_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_compteur_nbits_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_compteur_nbits_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_compteur_nbits_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_compteur_nbits_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_compteur_nbits_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_compteur_nbits_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:compteur_nbits:1.0 + + + nbits + Nbits + 7 + + + Component_Name + design_1_compteur_nbits_0_0 + + + + + compteur_nbits_v1_0 + module_ref + 1 + + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd new file mode 100644 index 0000000..c58480b --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd @@ -0,0 +1,98 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_compteur_nbits_0_0 IS + PORT ( + clk : IN STD_LOGIC; + i_en : IN STD_LOGIC; + reset : IN STD_LOGIC; + o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); +END design_1_compteur_nbits_0_0; + +ARCHITECTURE design_1_compteur_nbits_0_0_arch OF design_1_compteur_nbits_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT compteur_nbits IS + GENERIC ( + nbits : INTEGER + ); + PORT ( + clk : IN STD_LOGIC; + i_en : IN STD_LOGIC; + reset : IN STD_LOGIC; + o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); + END COMPONENT compteur_nbits; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; +BEGIN + U0 : compteur_nbits + GENERIC MAP ( + nbits => 7 + ) + PORT MAP ( + clk => clk, + i_en => i_en, + reset => reset, + o_val_cpt => o_val_cpt + ); +END design_1_compteur_nbits_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/synth/design_1_compteur_nbits_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/synth/design_1_compteur_nbits_0_0.vhd new file mode 100644 index 0000000..234773a --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/synth/design_1_compteur_nbits_0_0.vhd @@ -0,0 +1,104 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_compteur_nbits_0_0 IS + PORT ( + clk : IN STD_LOGIC; + i_en : IN STD_LOGIC; + reset : IN STD_LOGIC; + o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); +END design_1_compteur_nbits_0_0; + +ARCHITECTURE design_1_compteur_nbits_0_0_arch OF design_1_compteur_nbits_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT compteur_nbits IS + GENERIC ( + nbits : INTEGER + ); + PORT ( + clk : IN STD_LOGIC; + i_en : IN STD_LOGIC; + reset : IN STD_LOGIC; + o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); + END COMPONENT compteur_nbits; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "compteur_nbits,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_compteur_nbits_0_0_arch : ARCHITECTURE IS "design_1_compteur_nbits_0_0,compteur_nbits,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "design_1_compteur_nbits_0_0,compteur_nbits,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=compteur_nbits,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,nbits=7}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; +BEGIN + U0 : compteur_nbits + GENERIC MAP ( + nbits => 7 + ) + PORT MAP ( + clk => clk, + i_en => i_en, + reset => reset, + o_val_cpt => o_val_cpt + ); +END design_1_compteur_nbits_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0_1/design_1_compteur_nbits_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0_1/design_1_compteur_nbits_0_0.xml new file mode 100644 index 0000000..bba6fde --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0_1/design_1_compteur_nbits_0_0.xml @@ -0,0 +1,216 @@ + + + xilinx.com + customized_ip + design_1_compteur_nbits_0_0 + 1.0 + + + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + clk + + in + + + std_logic + dummy_view + + + + + + i_en + + in + + + std_logic + dummy_view + + + + + + reset + + in + + + std_logic + dummy_view + + + + + + o_val_cpt + + out + + 6 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + nbits + Nbits + 7 + + + + xilinx.com:module_ref:compteur_nbits:1.0 + + + nbits + Nbits + 7 + + + Component_Name + design_1_compteur_nbits_0_0 + + + + + compteur_nbits_v1_0 + module_ref + 1 + + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.dcp new file mode 100644 index 0000000..b63fb8a Binary files /dev/null and b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.dcp differ diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.xml new file mode 100644 index 0000000..7d71334 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.xml @@ -0,0 +1,369 @@ + + + xilinx.com + customized_ip + design_1_compteur_nbits_0_1 + 1.0 + + + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + compteur_nbits + + + outputProductCRC + 9:a0b2ffab + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_compteur_nbits_0_1 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:a0b2ffab + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + compteur_nbits + + + outputProductCRC + 9:cdf2cb27 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:cdf2cb27 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_compteur_nbits_0_1 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:cdf2cb27 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Tue Jan 16 16:58:52 UTC 2024 + + + outputProductCRC + 9:cdf2cb27 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_val_cpt + + out + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + nbits + Nbits + 7 + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_compteur_nbits_0_1.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_compteur_nbits_0_1.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_compteur_nbits_0_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_compteur_nbits_0_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_compteur_nbits_0_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_compteur_nbits_0_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_compteur_nbits_0_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:compteur_nbits:1.0 + + + nbits + Nbits + 7 + + + Component_Name + design_1_compteur_nbits_0_1 + + + + + compteur_nbits_v1_0 + module_ref + 1 + + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_sim_netlist.v new file mode 100644 index 0000000..453bb6f --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_sim_netlist.v @@ -0,0 +1,250 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 11:58:52 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_sim_netlist.v +// Design : design_1_compteur_nbits_0_1 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "design_1_compteur_nbits_0_1,compteur_nbits,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) +(* x_core_info = "compteur_nbits,Vivado 2020.2" *) +(* NotValidForBitStream *) +module design_1_compteur_nbits_0_1 + (clk, + i_en, + reset, + o_val_cpt); + (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0" *) input clk; + input i_en; + (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset; + output [6:0]o_val_cpt; + + wire clk; + wire i_en; + wire [6:0]o_val_cpt; + wire reset; + + design_1_compteur_nbits_0_1_compteur_nbits U0 + (.clk(clk), + .i_en(i_en), + .out(o_val_cpt), + .reset(reset)); +endmodule + +(* ORIG_REF_NAME = "compteur_nbits" *) +module design_1_compteur_nbits_0_1_compteur_nbits + (out, + i_en, + clk, + reset); + output [6:0]out; + input i_en; + input clk; + input reset; + + wire clk; + wire \d_val_cpt[6]_i_2_n_0 ; + wire i_en; + wire [6:0]out; + wire [6:0]plusOp; + wire reset; + + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT1 #( + .INIT(2'h1)) + \d_val_cpt[0]_i_1 + (.I0(out[0]), + .O(plusOp[0])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h6)) + \d_val_cpt[1]_i_1 + (.I0(out[0]), + .I1(out[1]), + .O(plusOp[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'h78)) + \d_val_cpt[2]_i_1 + (.I0(out[0]), + .I1(out[1]), + .I2(out[2]), + .O(plusOp[2])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h7F80)) + \d_val_cpt[3]_i_1 + (.I0(out[1]), + .I1(out[0]), + .I2(out[2]), + .I3(out[3]), + .O(plusOp[3])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \d_val_cpt[4]_i_1 + (.I0(out[2]), + .I1(out[0]), + .I2(out[1]), + .I3(out[3]), + .I4(out[4]), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \d_val_cpt[5]_i_1 + (.I0(out[3]), + .I1(out[1]), + .I2(out[0]), + .I3(out[2]), + .I4(out[4]), + .I5(out[5]), + .O(plusOp[5])); + LUT3 #( + .INIT(8'h78)) + \d_val_cpt[6]_i_1 + (.I0(\d_val_cpt[6]_i_2_n_0 ), + .I1(out[5]), + .I2(out[6]), + .O(plusOp[6])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h80000000)) + \d_val_cpt[6]_i_2 + (.I0(out[4]), + .I1(out[2]), + .I2(out[0]), + .I3(out[1]), + .I4(out[3]), + .O(\d_val_cpt[6]_i_2_n_0 )); + FDCE \d_val_cpt_reg[0] + (.C(clk), + .CE(i_en), + .CLR(reset), + .D(plusOp[0]), + .Q(out[0])); + FDCE \d_val_cpt_reg[1] + (.C(clk), + .CE(i_en), + .CLR(reset), + .D(plusOp[1]), + .Q(out[1])); + FDCE \d_val_cpt_reg[2] + (.C(clk), + .CE(i_en), + .CLR(reset), + .D(plusOp[2]), + .Q(out[2])); + FDCE \d_val_cpt_reg[3] + (.C(clk), + .CE(i_en), + .CLR(reset), + .D(plusOp[3]), + .Q(out[3])); + FDCE \d_val_cpt_reg[4] + (.C(clk), + .CE(i_en), + .CLR(reset), + .D(plusOp[4]), + .Q(out[4])); + FDCE \d_val_cpt_reg[5] + (.C(clk), + .CE(i_en), + .CLR(reset), + .D(plusOp[5]), + .Q(out[5])); + FDCE \d_val_cpt_reg[6] + (.C(clk), + .CE(i_en), + .CLR(reset), + .D(plusOp[6]), + .Q(out[6])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_stub.v new file mode 100644 index 0000000..010bb75 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_stub.v @@ -0,0 +1,23 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 11:58:52 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_stub.v +// Design : design_1_compteur_nbits_0_1 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "compteur_nbits,Vivado 2020.2" *) +module design_1_compteur_nbits_0_1(clk, i_en, reset, o_val_cpt) +/* synthesis syn_black_box black_box_pad_pin="clk,i_en,reset,o_val_cpt[6:0]" */; + input clk; + input i_en; + input reset; + output [6:0]o_val_cpt; +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd new file mode 100644 index 0000000..efc345f --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd @@ -0,0 +1,98 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_compteur_nbits_0_1 IS + PORT ( + clk : IN STD_LOGIC; + i_en : IN STD_LOGIC; + reset : IN STD_LOGIC; + o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); +END design_1_compteur_nbits_0_1; + +ARCHITECTURE design_1_compteur_nbits_0_1_arch OF design_1_compteur_nbits_0_1 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "yes"; + COMPONENT compteur_nbits IS + GENERIC ( + nbits : INTEGER + ); + PORT ( + clk : IN STD_LOGIC; + i_en : IN STD_LOGIC; + reset : IN STD_LOGIC; + o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); + END COMPONENT compteur_nbits; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; +BEGIN + U0 : compteur_nbits + GENERIC MAP ( + nbits => 7 + ) + PORT MAP ( + clk => clk, + i_en => i_en, + reset => reset, + o_val_cpt => o_val_cpt + ); +END design_1_compteur_nbits_0_1_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/synth/design_1_compteur_nbits_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/synth/design_1_compteur_nbits_0_1.vhd new file mode 100644 index 0000000..9965f7a --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/synth/design_1_compteur_nbits_0_1.vhd @@ -0,0 +1,104 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_compteur_nbits_0_1 IS + PORT ( + clk : IN STD_LOGIC; + i_en : IN STD_LOGIC; + reset : IN STD_LOGIC; + o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); +END design_1_compteur_nbits_0_1; + +ARCHITECTURE design_1_compteur_nbits_0_1_arch OF design_1_compteur_nbits_0_1 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "yes"; + COMPONENT compteur_nbits IS + GENERIC ( + nbits : INTEGER + ); + PORT ( + clk : IN STD_LOGIC; + i_en : IN STD_LOGIC; + reset : IN STD_LOGIC; + o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); + END COMPONENT compteur_nbits; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "compteur_nbits,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_compteur_nbits_0_1_arch : ARCHITECTURE IS "design_1_compteur_nbits_0_1,compteur_nbits,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "design_1_compteur_nbits_0_1,compteur_nbits,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=compteur_nbits,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,nbits=7}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; +BEGIN + U0 : compteur_nbits + GENERIC MAP ( + nbits => 7 + ) + PORT MAP ( + clk => clk, + i_en => i_en, + reset => reset, + o_val_cpt => o_val_cpt + ); +END design_1_compteur_nbits_0_1_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/design_1_mef_cod_i2s_vsb_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/design_1_mef_cod_i2s_vsb_0_0.xml new file mode 100644 index 0000000..41f23c5 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/design_1_mef_cod_i2s_vsb_0_0.xml @@ -0,0 +1,359 @@ + + + xilinx.com + customized_ip + design_1_mef_cod_i2s_vsb_0_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + o_cpt_bit_reset + + + + + + + RST + + + o_cpt_bit_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + mef_cod_i2s_vsb + + + outputProductCRC + 9:8a0fb88c + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_mef_cod_i2s_vsb_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:8a0fb88c + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + mef_cod_i2s_vsb + + + outputProductCRC + 9:89a9abf5 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:89a9abf5 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_mef_cod_i2s_vsb_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:89a9abf5 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:89a9abf5 + + + + + + + i_bclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_lrc + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_cpt_bits + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_bit_enable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_load_left + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_load_right + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_cpt_bit_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_mef_cod_i2s_vsb_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_mef_cod_i2s_vsb_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_mef_cod_i2s_vsb_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_mef_cod_i2s_vsb_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_mef_cod_i2s_vsb_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_mef_cod_i2s_vsb_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_mef_cod_i2s_vsb_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:mef_cod_i2s_vsb:1.0 + + + Component_Name + design_1_mef_cod_i2s_vsb_0_0 + + + + + mef_cod_i2s_vsb_v1_0 + module_ref + 1 + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd new file mode 100644 index 0000000..9f669ea --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd @@ -0,0 +1,104 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:mef_cod_i2s_vsb:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_mef_cod_i2s_vsb_0_0 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_lrc : IN STD_LOGIC; + i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + o_bit_enable : OUT STD_LOGIC; + o_load_left : OUT STD_LOGIC; + o_load_right : OUT STD_LOGIC; + o_cpt_bit_reset : OUT STD_LOGIC + ); +END design_1_mef_cod_i2s_vsb_0_0; + +ARCHITECTURE design_1_mef_cod_i2s_vsb_0_0_arch OF design_1_mef_cod_i2s_vsb_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT mef_cod_i2s_vsb IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_lrc : IN STD_LOGIC; + i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + o_bit_enable : OUT STD_LOGIC; + o_load_left : OUT STD_LOGIC; + o_load_right : OUT STD_LOGIC; + o_cpt_bit_reset : OUT STD_LOGIC + ); + END COMPONENT mef_cod_i2s_vsb; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; +BEGIN + U0 : mef_cod_i2s_vsb + PORT MAP ( + i_bclk => i_bclk, + i_reset => i_reset, + i_lrc => i_lrc, + i_cpt_bits => i_cpt_bits, + o_bit_enable => o_bit_enable, + o_load_left => o_load_left, + o_load_right => o_load_right, + o_cpt_bit_reset => o_cpt_bit_reset + ); +END design_1_mef_cod_i2s_vsb_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/synth/design_1_mef_cod_i2s_vsb_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/synth/design_1_mef_cod_i2s_vsb_0_0.vhd new file mode 100644 index 0000000..5cf3090 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/synth/design_1_mef_cod_i2s_vsb_0_0.vhd @@ -0,0 +1,110 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:mef_cod_i2s_vsb:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_mef_cod_i2s_vsb_0_0 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_lrc : IN STD_LOGIC; + i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + o_bit_enable : OUT STD_LOGIC; + o_load_left : OUT STD_LOGIC; + o_load_right : OUT STD_LOGIC; + o_cpt_bit_reset : OUT STD_LOGIC + ); +END design_1_mef_cod_i2s_vsb_0_0; + +ARCHITECTURE design_1_mef_cod_i2s_vsb_0_0_arch OF design_1_mef_cod_i2s_vsb_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT mef_cod_i2s_vsb IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_lrc : IN STD_LOGIC; + i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + o_bit_enable : OUT STD_LOGIC; + o_load_left : OUT STD_LOGIC; + o_load_right : OUT STD_LOGIC; + o_cpt_bit_reset : OUT STD_LOGIC + ); + END COMPONENT mef_cod_i2s_vsb; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "mef_cod_i2s_vsb,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mef_cod_i2s_vsb_0_0_arch : ARCHITECTURE IS "design_1_mef_cod_i2s_vsb_0_0,mef_cod_i2s_vsb,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "design_1_mef_cod_i2s_vsb_0_0,mef_cod_i2s_vsb,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mef_cod_i2s_vsb,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; +BEGIN + U0 : mef_cod_i2s_vsb + PORT MAP ( + i_bclk => i_bclk, + i_reset => i_reset, + i_lrc => i_lrc, + i_cpt_bits => i_cpt_bits, + o_bit_enable => o_bit_enable, + o_load_left => o_load_left, + o_load_right => o_load_right, + o_cpt_bit_reset => o_cpt_bit_reset + ); +END design_1_mef_cod_i2s_vsb_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xml new file mode 100644 index 0000000..0617352 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xml @@ -0,0 +1,206 @@ + + + xilinx.com + customized_ip + design_1_mef_cod_i2s_vsb_0_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + o_cpt_bit_reset + + + + + + + RST + + + o_cpt_bit_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + i_bclk + + in + + + std_logic + dummy_view + + + + + + i_reset + + in + + + std_logic + dummy_view + + + + + + i_lrc + + in + + + std_logic + dummy_view + + + + + + i_cpt_bits + + in + + 6 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_bit_enable + + out + + + std_logic + dummy_view + + + + + + o_load_left + + out + + + std_logic + dummy_view + + + + + + o_load_right + + out + + + std_logic + dummy_view + + + + + + o_cpt_bit_reset + + out + + + std_logic + dummy_view + + + + + + + xilinx.com:module_ref:mef_cod_i2s_vsb:1.0 + + + Component_Name + design_1_mef_cod_i2s_vsb_0_0 + + + + + mef_cod_i2s_vsb_v1_0 + module_ref + 1 + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/design_1_mef_decod_i2s_v1b_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/design_1_mef_decod_i2s_v1b_0_0.xml new file mode 100644 index 0000000..286ae5e --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/design_1_mef_decod_i2s_v1b_0_0.xml @@ -0,0 +1,372 @@ + + + xilinx.com + customized_ip + design_1_mef_decod_i2s_v1b_0_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + o_cpt_bit_reset + + + + + + + RST + + + o_cpt_bit_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + mef_decod_i2s_v1b + + + outputProductCRC + 9:75902b07 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_mef_decod_i2s_v1b_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:75902b07 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + mef_decod_i2s_v1b + + + outputProductCRC + 9:a9bc969e + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:a9bc969e + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_mef_decod_i2s_v1b_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:a9bc969e + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:a9bc969e + + + + + + + i_bclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_lrc + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_cpt_bits + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_bit_enable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_load_left + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_load_right + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_str_dat + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_cpt_bit_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_mef_decod_i2s_v1b_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_mef_decod_i2s_v1b_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_mef_decod_i2s_v1b_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_mef_decod_i2s_v1b_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_mef_decod_i2s_v1b_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_mef_decod_i2s_v1b_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_mef_decod_i2s_v1b_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:mef_decod_i2s_v1b:1.0 + + + Component_Name + design_1_mef_decod_i2s_v1b_0_0 + + + + + mef_decod_i2s_v1b_v1_0 + module_ref + 1 + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd new file mode 100644 index 0000000..63454ae --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd @@ -0,0 +1,107 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:mef_decod_i2s_v1b:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_mef_decod_i2s_v1b_0_0 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_lrc : IN STD_LOGIC; + i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + o_bit_enable : OUT STD_LOGIC; + o_load_left : OUT STD_LOGIC; + o_load_right : OUT STD_LOGIC; + o_str_dat : OUT STD_LOGIC; + o_cpt_bit_reset : OUT STD_LOGIC + ); +END design_1_mef_decod_i2s_v1b_0_0; + +ARCHITECTURE design_1_mef_decod_i2s_v1b_0_0_arch OF design_1_mef_decod_i2s_v1b_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT mef_decod_i2s_v1b IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_lrc : IN STD_LOGIC; + i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + o_bit_enable : OUT STD_LOGIC; + o_load_left : OUT STD_LOGIC; + o_load_right : OUT STD_LOGIC; + o_str_dat : OUT STD_LOGIC; + o_cpt_bit_reset : OUT STD_LOGIC + ); + END COMPONENT mef_decod_i2s_v1b; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; +BEGIN + U0 : mef_decod_i2s_v1b + PORT MAP ( + i_bclk => i_bclk, + i_reset => i_reset, + i_lrc => i_lrc, + i_cpt_bits => i_cpt_bits, + o_bit_enable => o_bit_enable, + o_load_left => o_load_left, + o_load_right => o_load_right, + o_str_dat => o_str_dat, + o_cpt_bit_reset => o_cpt_bit_reset + ); +END design_1_mef_decod_i2s_v1b_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/synth/design_1_mef_decod_i2s_v1b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/synth/design_1_mef_decod_i2s_v1b_0_0.vhd new file mode 100644 index 0000000..d6f2bc5 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/synth/design_1_mef_decod_i2s_v1b_0_0.vhd @@ -0,0 +1,113 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:mef_decod_i2s_v1b:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_mef_decod_i2s_v1b_0_0 IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_lrc : IN STD_LOGIC; + i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + o_bit_enable : OUT STD_LOGIC; + o_load_left : OUT STD_LOGIC; + o_load_right : OUT STD_LOGIC; + o_str_dat : OUT STD_LOGIC; + o_cpt_bit_reset : OUT STD_LOGIC + ); +END design_1_mef_decod_i2s_v1b_0_0; + +ARCHITECTURE design_1_mef_decod_i2s_v1b_0_0_arch OF design_1_mef_decod_i2s_v1b_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT mef_decod_i2s_v1b IS + PORT ( + i_bclk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_lrc : IN STD_LOGIC; + i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + o_bit_enable : OUT STD_LOGIC; + o_load_left : OUT STD_LOGIC; + o_load_right : OUT STD_LOGIC; + o_str_dat : OUT STD_LOGIC; + o_cpt_bit_reset : OUT STD_LOGIC + ); + END COMPONENT mef_decod_i2s_v1b; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "mef_decod_i2s_v1b,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mef_decod_i2s_v1b_0_0_arch : ARCHITECTURE IS "design_1_mef_decod_i2s_v1b_0_0,mef_decod_i2s_v1b,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "design_1_mef_decod_i2s_v1b_0_0,mef_decod_i2s_v1b,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mef_decod_i2s_v1b,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; +BEGIN + U0 : mef_decod_i2s_v1b + PORT MAP ( + i_bclk => i_bclk, + i_reset => i_reset, + i_lrc => i_lrc, + i_cpt_bits => i_cpt_bits, + o_bit_enable => o_bit_enable, + o_load_left => o_load_left, + o_load_right => o_load_right, + o_str_dat => o_str_dat, + o_cpt_bit_reset => o_cpt_bit_reset + ); +END design_1_mef_decod_i2s_v1b_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/design_1_module_commande_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/design_1_module_commande_0_0.xml new file mode 100644 index 0000000..d2cc413 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/design_1_module_commande_0_0.xml @@ -0,0 +1,434 @@ + + + xilinx.com + customized_ip + design_1_module_commande_0_0 + 1.0 + + + o_reset + + + + + + + RST + + + o_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + clk + + + + + + + CLK + + + clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + module_commande + + + outputProductCRC + 9:798ced9e + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_module_commande_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:48:36 UTC 2024 + + + outputProductCRC + 9:798ced9e + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + module_commande + + + outputProductCRC + 9:fa176fa8 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:fa176fa8 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_module_commande_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:fa176fa8 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:fa176fa8 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_btn + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_sw + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_btn_cd + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_selection_fct + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_selection_par + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + nbtn + Nbtn + 4 + + + mode_simulation + Mode Simulation + "0" + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_module_commande_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_module_commande_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_module_commande_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_module_commande_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_module_commande_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_module_commande_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_module_commande_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:module_commande:1.0 + + + nbtn + Nbtn + 4 + + + mode_simulation + Mode Simulation + "0" + + + Component_Name + design_1_module_commande_0_0 + + + + + module_commande_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd new file mode 100644 index 0000000..643d8ee --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd @@ -0,0 +1,109 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:module_commande:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_module_commande_0_0 IS + PORT ( + clk : IN STD_LOGIC; + o_reset : OUT STD_LOGIC; + i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); +END design_1_module_commande_0_0; + +ARCHITECTURE design_1_module_commande_0_0_arch OF design_1_module_commande_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT module_commande IS + GENERIC ( + nbtn : INTEGER; + mode_simulation : STD_LOGIC + ); + PORT ( + clk : IN STD_LOGIC; + o_reset : OUT STD_LOGIC; + i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + END COMPONENT module_commande; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF o_reset: SIGNAL IS "XIL_INTERFACENAME o_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF o_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; +BEGIN + U0 : module_commande + GENERIC MAP ( + nbtn => 4, + mode_simulation => '0' + ) + PORT MAP ( + clk => clk, + o_reset => o_reset, + i_btn => i_btn, + i_sw => i_sw, + o_btn_cd => o_btn_cd, + o_selection_fct => o_selection_fct, + o_selection_par => o_selection_par + ); +END design_1_module_commande_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/synth/design_1_module_commande_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/synth/design_1_module_commande_0_0.vhd new file mode 100644 index 0000000..68509bc --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/synth/design_1_module_commande_0_0.vhd @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:module_commande:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_module_commande_0_0 IS + PORT ( + clk : IN STD_LOGIC; + o_reset : OUT STD_LOGIC; + i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); +END design_1_module_commande_0_0; + +ARCHITECTURE design_1_module_commande_0_0_arch OF design_1_module_commande_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT module_commande IS + GENERIC ( + nbtn : INTEGER; + mode_simulation : STD_LOGIC + ); + PORT ( + clk : IN STD_LOGIC; + o_reset : OUT STD_LOGIC; + i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + END COMPONENT module_commande; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "module_commande,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_module_commande_0_0_arch : ARCHITECTURE IS "design_1_module_commande_0_0,module_commande,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "design_1_module_commande_0_0,module_commande,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=module_commande,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,nbtn=4,mode_simulation=0}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF o_reset: SIGNAL IS "XIL_INTERFACENAME o_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF o_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; +BEGIN + U0 : module_commande + GENERIC MAP ( + nbtn => 4, + mode_simulation => '0' + ) + PORT MAP ( + clk => clk, + o_reset => o_reset, + i_btn => i_btn, + i_sw => i_sw, + o_btn_cd => o_btn_cd, + o_selection_fct => o_selection_fct, + o_selection_par => o_selection_par + ); +END design_1_module_commande_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.dcp new file mode 100644 index 0000000..86264d3 Binary files /dev/null and b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.dcp differ diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.xml new file mode 100644 index 0000000..7833c19 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.xml @@ -0,0 +1,257 @@ + + + xilinx.com + customized_ip + design_1_mux2_0_0 + 1.0 + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + mux2 + + + outputProductCRC + 9:2d84ddc4 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_mux2_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:2d84ddc4 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + mux2 + + + outputProductCRC + 9:09e1266e + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:09e1266e + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_mux2_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:09e1266e + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Tue Jan 16 17:01:55 UTC 2024 + + + outputProductCRC + 9:09e1266e + + + + + + + sel + + in + + 1 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + input1 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + input2 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + output0 + + out + + 23 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + input_length + Input Length + 24 + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_mux2_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_mux2_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_mux2_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_mux2_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_mux2_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_mux2_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_mux2_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:mux2:1.0 + + + input_length + Input Length + 24 + + + Component_Name + design_1_mux2_0_0 + + + + + mux2_v1_0 + module_ref + 1 + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_sim_netlist.v new file mode 100644 index 0000000..1d2b0f4 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_sim_netlist.v @@ -0,0 +1,331 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 12:01:55 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_sim_netlist.v +// Design : design_1_mux2_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "design_1_mux2_0_0,mux2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) +(* x_core_info = "mux2,Vivado 2020.2" *) +(* NotValidForBitStream *) +module design_1_mux2_0_0 + (sel, + input1, + input2, + output0); + input [1:0]sel; + input [23:0]input1; + input [23:0]input2; + output [23:0]output0; + + wire [23:0]input1; + wire [23:0]input2; + wire [23:0]output0; + wire [1:0]sel; + + design_1_mux2_0_0_mux2 U0 + (.input1(input1), + .input2(input2), + .output0(output0), + .sel(sel)); +endmodule + +(* ORIG_REF_NAME = "mux2" *) +module design_1_mux2_0_0_mux2 + (output0, + input1, + sel, + input2); + output [23:0]output0; + input [23:0]input1; + input [1:0]sel; + input [23:0]input2; + + wire [23:0]input1; + wire [23:0]input2; + wire [23:0]output0; + wire [1:0]sel; + + LUT4 #( + .INIT(16'h3808)) + \output0[0]_INST_0 + (.I0(input1[0]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[0]), + .O(output0[0])); + LUT4 #( + .INIT(16'h3808)) + \output0[10]_INST_0 + (.I0(input1[10]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[10]), + .O(output0[10])); + LUT4 #( + .INIT(16'h3808)) + \output0[11]_INST_0 + (.I0(input1[11]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[11]), + .O(output0[11])); + LUT4 #( + .INIT(16'h3808)) + \output0[12]_INST_0 + (.I0(input1[12]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[12]), + .O(output0[12])); + LUT4 #( + .INIT(16'h3808)) + \output0[13]_INST_0 + (.I0(input1[13]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[13]), + .O(output0[13])); + LUT4 #( + .INIT(16'h3808)) + \output0[14]_INST_0 + (.I0(input1[14]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[14]), + .O(output0[14])); + LUT4 #( + .INIT(16'h3808)) + \output0[15]_INST_0 + (.I0(input1[15]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[15]), + .O(output0[15])); + LUT4 #( + .INIT(16'h3808)) + \output0[16]_INST_0 + (.I0(input1[16]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[16]), + .O(output0[16])); + LUT4 #( + .INIT(16'h3808)) + \output0[17]_INST_0 + (.I0(input1[17]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[17]), + .O(output0[17])); + LUT4 #( + .INIT(16'h3808)) + \output0[18]_INST_0 + (.I0(input1[18]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[18]), + .O(output0[18])); + LUT4 #( + .INIT(16'h3808)) + \output0[19]_INST_0 + (.I0(input1[19]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[19]), + .O(output0[19])); + LUT4 #( + .INIT(16'h3808)) + \output0[1]_INST_0 + (.I0(input1[1]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[1]), + .O(output0[1])); + LUT4 #( + .INIT(16'h3808)) + \output0[20]_INST_0 + (.I0(input1[20]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[20]), + .O(output0[20])); + LUT4 #( + .INIT(16'h3808)) + \output0[21]_INST_0 + (.I0(input1[21]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[21]), + .O(output0[21])); + LUT4 #( + .INIT(16'h3808)) + \output0[22]_INST_0 + (.I0(input1[22]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[22]), + .O(output0[22])); + LUT4 #( + .INIT(16'h3808)) + \output0[23]_INST_0 + (.I0(input1[23]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[23]), + .O(output0[23])); + LUT4 #( + .INIT(16'h3808)) + \output0[2]_INST_0 + (.I0(input1[2]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[2]), + .O(output0[2])); + LUT4 #( + .INIT(16'h3808)) + \output0[3]_INST_0 + (.I0(input1[3]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[3]), + .O(output0[3])); + LUT4 #( + .INIT(16'h3808)) + \output0[4]_INST_0 + (.I0(input1[4]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[4]), + .O(output0[4])); + LUT4 #( + .INIT(16'h3808)) + \output0[5]_INST_0 + (.I0(input1[5]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[5]), + .O(output0[5])); + LUT4 #( + .INIT(16'h3808)) + \output0[6]_INST_0 + (.I0(input1[6]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[6]), + .O(output0[6])); + LUT4 #( + .INIT(16'h3808)) + \output0[7]_INST_0 + (.I0(input1[7]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[7]), + .O(output0[7])); + LUT4 #( + .INIT(16'h3808)) + \output0[8]_INST_0 + (.I0(input1[8]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[8]), + .O(output0[8])); + LUT4 #( + .INIT(16'h3808)) + \output0[9]_INST_0 + (.I0(input1[9]), + .I1(sel[0]), + .I2(sel[1]), + .I3(input2[9]), + .O(output0[9])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_stub.v new file mode 100644 index 0000000..56c6bce --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_stub.v @@ -0,0 +1,23 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 12:01:55 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_stub.v +// Design : design_1_mux2_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "mux2,Vivado 2020.2" *) +module design_1_mux2_0_0(sel, input1, input2, output0) +/* synthesis syn_black_box black_box_pad_pin="sel[1:0],input1[23:0],input2[23:0],output0[23:0]" */; + input [1:0]sel; + input [23:0]input1; + input [23:0]input2; + output [23:0]output0; +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd new file mode 100644 index 0000000..ffe2904 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd @@ -0,0 +1,92 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:mux2:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_mux2_0_0 IS + PORT ( + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_mux2_0_0; + +ARCHITECTURE design_1_mux2_0_0_arch OF design_1_mux2_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux2_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT mux2 IS + GENERIC ( + input_length : INTEGER + ); + PORT ( + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT mux2; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux2_0_0_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : mux2 + GENERIC MAP ( + input_length => 24 + ) + PORT MAP ( + sel => sel, + input1 => input1, + input2 => input2, + output0 => output0 + ); +END design_1_mux2_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/synth/design_1_mux2_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/synth/design_1_mux2_0_0.vhd new file mode 100644 index 0000000..c248b9c --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/synth/design_1_mux2_0_0.vhd @@ -0,0 +1,98 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:mux2:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_mux2_0_0 IS + PORT ( + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_mux2_0_0; + +ARCHITECTURE design_1_mux2_0_0_arch OF design_1_mux2_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux2_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT mux2 IS + GENERIC ( + input_length : INTEGER + ); + PORT ( + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT mux2; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_mux2_0_0_arch: ARCHITECTURE IS "mux2,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mux2_0_0_arch : ARCHITECTURE IS "design_1_mux2_0_0,mux2,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_mux2_0_0_arch: ARCHITECTURE IS "design_1_mux2_0_0,mux2,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mux2,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,input_length=24}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux2_0_0_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : mux2 + GENERIC MAP ( + input_length => 24 + ) + PORT MAP ( + sel => sel, + input1 => input1, + input2 => input2, + output0 => output0 + ); +END design_1_mux2_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0_1/design_1_mux2_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0_1/design_1_mux2_0_0.xml new file mode 100644 index 0000000..cc1c721 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0_1/design_1_mux2_0_0.xml @@ -0,0 +1,104 @@ + + + xilinx.com + customized_ip + design_1_mux2_0_0 + 1.0 + + + + sel + + in + + 1 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + input1 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + input2 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + output0 + + out + + 23 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + + + input_length + Input Length + 24 + + + + xilinx.com:module_ref:mux2:1.0 + + + input_length + Input Length + 24 + + + Component_Name + design_1_mux2_0_0 + + + + + mux2_v1_0 + module_ref + 1 + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/design_1_mux4_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/design_1_mux4_0_0.xml new file mode 100644 index 0000000..959e149 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/design_1_mux4_0_0.xml @@ -0,0 +1,287 @@ + + + xilinx.com + customized_ip + design_1_mux4_0_0 + 1.0 + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + mux4 + + + outputProductCRC + 9:c024d4a4 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_mux4_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:c024d4a4 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + mux4 + + + outputProductCRC + 9:95f3fa1f + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:95f3fa1f + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_mux4_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:95f3fa1f + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:95f3fa1f + + + + + + + input0 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + input1 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + input2 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + input3 + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sel + + in + + 1 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + output0 + + out + + 23 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + input_length + Input Length + 24 + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_mux4_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_mux4_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_mux4_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_mux4_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_mux4_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_mux4_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_mux4_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:mux4:1.0 + + + input_length + Input Length + 24 + + + Component_Name + design_1_mux4_0_0 + + + + + mux4_v1_0 + module_ref + 1 + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd new file mode 100644 index 0000000..ae6ac28 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd @@ -0,0 +1,98 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:mux4:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_mux4_0_0 IS + PORT ( + input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_mux4_0_0; + +ARCHITECTURE design_1_mux4_0_0_arch OF design_1_mux4_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT mux4 IS + GENERIC ( + input_length : INTEGER + ); + PORT ( + input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT mux4; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_0_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : mux4 + GENERIC MAP ( + input_length => 24 + ) + PORT MAP ( + input0 => input0, + input1 => input1, + input2 => input2, + input3 => input3, + sel => sel, + output0 => output0 + ); +END design_1_mux4_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/synth/design_1_mux4_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/synth/design_1_mux4_0_0.vhd new file mode 100644 index 0000000..f3272f1 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/synth/design_1_mux4_0_0.vhd @@ -0,0 +1,104 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:mux4:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_mux4_0_0 IS + PORT ( + input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_mux4_0_0; + +ARCHITECTURE design_1_mux4_0_0_arch OF design_1_mux4_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT mux4 IS + GENERIC ( + input_length : INTEGER + ); + PORT ( + input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT mux4; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_mux4_0_0_arch: ARCHITECTURE IS "mux4,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mux4_0_0_arch : ARCHITECTURE IS "design_1_mux4_0_0,mux4,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_mux4_0_0_arch: ARCHITECTURE IS "design_1_mux4_0_0,mux4,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mux4,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,input_length=24}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_0_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : mux4 + GENERIC MAP ( + input_length => 24 + ) + PORT MAP ( + input0 => input0, + input1 => input1, + input2 => input2, + input3 => input3, + sel => sel, + output0 => output0 + ); +END design_1_mux4_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/design_1_mux4_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/design_1_mux4_0_1.xml new file mode 100644 index 0000000..01e4061 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/design_1_mux4_0_1.xml @@ -0,0 +1,290 @@ + + + xilinx.com + customized_ip + design_1_mux4_0_1 + 1.0 + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + mux4 + + + outputProductCRC + 9:29affc6f + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_mux4_0_1 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:29affc6f + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + mux4 + + + outputProductCRC + 9:25519e33 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:25519e33 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_mux4_0_1 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:25519e33 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:25519e33 + + + + + + + input0 + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + input1 + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + input2 + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + input3 + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sel + + in + + 1 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + output0 + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + input_length + Input Length + 8 + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_mux4_0_1.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_mux4_0_1.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_mux4_0_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_mux4_0_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_mux4_0_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_mux4_0_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_mux4_0_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:mux4:1.0 + + + input_length + Input Length + 8 + + + Component_Name + design_1_mux4_0_1 + + + + + mux4_v1_0 + module_ref + 1 + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd new file mode 100644 index 0000000..d30d1e5 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd @@ -0,0 +1,98 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:mux4:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_mux4_0_1 IS + PORT ( + input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END design_1_mux4_0_1; + +ARCHITECTURE design_1_mux4_0_1_arch OF design_1_mux4_0_1 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_1_arch: ARCHITECTURE IS "yes"; + COMPONENT mux4 IS + GENERIC ( + input_length : INTEGER + ); + PORT ( + input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT mux4; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_1_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : mux4 + GENERIC MAP ( + input_length => 8 + ) + PORT MAP ( + input0 => input0, + input1 => input1, + input2 => input2, + input3 => input3, + sel => sel, + output0 => output0 + ); +END design_1_mux4_0_1_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/synth/design_1_mux4_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/synth/design_1_mux4_0_1.vhd new file mode 100644 index 0000000..215809e --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/synth/design_1_mux4_0_1.vhd @@ -0,0 +1,104 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:mux4:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_mux4_0_1 IS + PORT ( + input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END design_1_mux4_0_1; + +ARCHITECTURE design_1_mux4_0_1_arch OF design_1_mux4_0_1 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_1_arch: ARCHITECTURE IS "yes"; + COMPONENT mux4 IS + GENERIC ( + input_length : INTEGER + ); + PORT ( + input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT mux4; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_mux4_0_1_arch: ARCHITECTURE IS "mux4,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mux4_0_1_arch : ARCHITECTURE IS "design_1_mux4_0_1,mux4,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_mux4_0_1_arch: ARCHITECTURE IS "design_1_mux4_0_1,mux4,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mux4,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,input_length=8}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_1_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : mux4 + GENERIC MAP ( + input_length => 8 + ) + PORT MAP ( + input0 => input0, + input1 => input1, + input2 => input2, + input3 => input3, + sel => sel, + output0 => output0 + ); +END design_1_mux4_0_1_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_parametre_0_0/design_1_parametre_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_parametre_0_0/design_1_parametre_0_0.xml new file mode 100644 index 0000000..888b6e5 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_parametre_0_0/design_1_parametre_0_0.xml @@ -0,0 +1,73 @@ + + + xilinx.com + customized_ip + design_1_parametre_0_0 + 1.0 + + + + dout + + out + + 7 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + CONST_WIDTH + Const Width + 8 + + + CONST_VAL + Const Val + 0x00 + + + + Gives a constant signed value. + + + Component_Name + design_1_parametre_0_0 + + + CONST_WIDTH + Const Width + 8 + + + CONST_VAL + Const Val + 0 + + + + + Constant + 7 + + + + + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/design_1_reg_24b_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/design_1_reg_24b_0_0.xml new file mode 100644 index 0000000..353467a --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/design_1_reg_24b_0_0.xml @@ -0,0 +1,369 @@ + + + xilinx.com + customized_ip + design_1_reg_24b_0_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + i_clk + + + + + + + CLK + + + i_clk + + + + + + ASSOCIATED_RESET + i_reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + reg_24b + + + outputProductCRC + 9:63b2073a + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_reg_24b_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:63b2073a + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + reg_24b + + + outputProductCRC + 9:2dafd90a + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:2dafd90a + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_reg_24b_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:2dafd90a + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:2dafd90a + + + + + + + i_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_dat + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_dat + + out + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_reg_24b_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_reg_24b_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_reg_24b_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_reg_24b_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_reg_24b_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_reg_24b_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_reg_24b_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:reg_24b:1.0 + + + Component_Name + design_1_reg_24b_0_0 + + + + + reg_24b_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd new file mode 100644 index 0000000..4ef9d64 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd @@ -0,0 +1,95 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_reg_24b_0_0 IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_reg_24b_0_0; + +ARCHITECTURE design_1_reg_24b_0_0_arch OF design_1_reg_24b_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT reg_24b IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT reg_24b; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK"; +BEGIN + U0 : reg_24b + PORT MAP ( + i_clk => i_clk, + i_reset => i_reset, + i_en => i_en, + i_dat => i_dat, + o_dat => o_dat + ); +END design_1_reg_24b_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/synth/design_1_reg_24b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/synth/design_1_reg_24b_0_0.vhd new file mode 100644 index 0000000..9e9d60f --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/synth/design_1_reg_24b_0_0.vhd @@ -0,0 +1,101 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_reg_24b_0_0 IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_reg_24b_0_0; + +ARCHITECTURE design_1_reg_24b_0_0_arch OF design_1_reg_24b_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT reg_24b IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT reg_24b; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "reg_24b,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_reg_24b_0_0_arch : ARCHITECTURE IS "design_1_reg_24b_0_0,reg_24b,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "design_1_reg_24b_0_0,reg_24b,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=reg_24b,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK"; +BEGIN + U0 : reg_24b + PORT MAP ( + i_clk => i_clk, + i_reset => i_reset, + i_en => i_en, + i_dat => i_dat, + o_dat => o_dat + ); +END design_1_reg_24b_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/design_1_reg_24b_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/design_1_reg_24b_0_1.xml new file mode 100644 index 0000000..a20b432 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/design_1_reg_24b_0_1.xml @@ -0,0 +1,369 @@ + + + xilinx.com + customized_ip + design_1_reg_24b_0_1 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + i_clk + + + + + + + CLK + + + i_clk + + + + + + ASSOCIATED_RESET + i_reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + reg_24b + + + outputProductCRC + 9:87279137 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_reg_24b_0_1 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:87279137 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + reg_24b + + + outputProductCRC + 9:b7bc7d08 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:b7bc7d08 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_reg_24b_0_1 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:b7bc7d08 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:b7bc7d08 + + + + + + + i_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_dat + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_dat + + out + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_reg_24b_0_1.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_reg_24b_0_1.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_reg_24b_0_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_reg_24b_0_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_reg_24b_0_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_reg_24b_0_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_reg_24b_0_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:reg_24b:1.0 + + + Component_Name + design_1_reg_24b_0_1 + + + + + reg_24b_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd new file mode 100644 index 0000000..3883a48 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd @@ -0,0 +1,95 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_reg_24b_0_1 IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_reg_24b_0_1; + +ARCHITECTURE design_1_reg_24b_0_1_arch OF design_1_reg_24b_0_1 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "yes"; + COMPONENT reg_24b IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT reg_24b; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK"; +BEGIN + U0 : reg_24b + PORT MAP ( + i_clk => i_clk, + i_reset => i_reset, + i_en => i_en, + i_dat => i_dat, + o_dat => o_dat + ); +END design_1_reg_24b_0_1_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/synth/design_1_reg_24b_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/synth/design_1_reg_24b_0_1.vhd new file mode 100644 index 0000000..978bba8 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/synth/design_1_reg_24b_0_1.vhd @@ -0,0 +1,101 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_reg_24b_0_1 IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_reg_24b_0_1; + +ARCHITECTURE design_1_reg_24b_0_1_arch OF design_1_reg_24b_0_1 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "yes"; + COMPONENT reg_24b IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT reg_24b; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "reg_24b,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_reg_24b_0_1_arch : ARCHITECTURE IS "design_1_reg_24b_0_1,reg_24b,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "design_1_reg_24b_0_1,reg_24b,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=reg_24b,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK"; +BEGIN + U0 : reg_24b + PORT MAP ( + i_clk => i_clk, + i_reset => i_reset, + i_en => i_en, + i_dat => i_dat, + o_dat => o_dat + ); +END design_1_reg_24b_0_1_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.dcp new file mode 100644 index 0000000..06da2bb Binary files /dev/null and b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.dcp differ diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.xml new file mode 100644 index 0000000..de17a04 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.xml @@ -0,0 +1,399 @@ + + + xilinx.com + customized_ip + design_1_reg_dec_24b_0_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + i_clk + + + + + + + CLK + + + i_clk + + + + + + ASSOCIATED_RESET + i_reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + reg_dec_24b + + + outputProductCRC + 9:2d5a01c5 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_reg_dec_24b_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:2d5a01c5 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + reg_dec_24b + + + outputProductCRC + 9:31fe9609 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:31fe9609 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_reg_dec_24b_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:31fe9609 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Tue Jan 16 16:58:52 UTC 2024 + + + outputProductCRC + 9:31fe9609 + + + + + + + i_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_load + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_dat_bit + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_dat_load + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_dat + + out + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_reg_dec_24b_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_reg_dec_24b_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_reg_dec_24b_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_reg_dec_24b_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_reg_dec_24b_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_reg_dec_24b_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_reg_dec_24b_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:reg_dec_24b:1.0 + + + Component_Name + design_1_reg_dec_24b_0_0 + + + + + reg_dec_24b_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_sim_netlist.v new file mode 100644 index 0000000..e7edd8b --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_sim_netlist.v @@ -0,0 +1,504 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 11:58:52 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_sim_netlist.v +// Design : design_1_reg_dec_24b_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "design_1_reg_dec_24b_0_0,reg_dec_24b,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) +(* x_core_info = "reg_dec_24b,Vivado 2020.2" *) +(* NotValidForBitStream *) +module design_1_reg_dec_24b_0_0 + (i_clk, + i_reset, + i_load, + i_en, + i_dat_bit, + i_dat_load, + o_dat); + (* x_interface_info = "xilinx.com:signal:clock:1.0 i_clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0" *) input i_clk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 i_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input i_reset; + input i_load; + input i_en; + input i_dat_bit; + input [23:0]i_dat_load; + output [23:0]o_dat; + + wire i_clk; + wire i_dat_bit; + wire [23:0]i_dat_load; + wire i_en; + wire i_load; + wire i_reset; + wire [23:0]o_dat; + + design_1_reg_dec_24b_0_0_reg_dec_24b U0 + (.i_clk(i_clk), + .i_dat_bit(i_dat_bit), + .i_dat_load(i_dat_load), + .i_en(i_en), + .i_load(i_load), + .i_reset(i_reset), + .o_dat(o_dat)); +endmodule + +(* ORIG_REF_NAME = "reg_dec_24b" *) +module design_1_reg_dec_24b_0_0_reg_dec_24b + (o_dat, + i_clk, + i_reset, + i_dat_load, + i_load, + i_dat_bit, + i_en); + output [23:0]o_dat; + input i_clk; + input i_reset; + input [23:0]i_dat_load; + input i_load; + input i_dat_bit; + input i_en; + + wire i_clk; + wire i_dat_bit; + wire [23:0]i_dat_load; + wire i_en; + wire i_load; + wire i_reset; + wire [23:0]o_dat; + wire [23:0]p_1_in; + wire \q_shift_reg[23]_i_1_n_0 ; + + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[0]_i_1 + (.I0(i_dat_load[0]), + .I1(i_load), + .I2(i_dat_bit), + .O(p_1_in[0])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[10]_i_1 + (.I0(i_dat_load[10]), + .I1(i_load), + .I2(o_dat[9]), + .O(p_1_in[10])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[11]_i_1 + (.I0(i_dat_load[11]), + .I1(i_load), + .I2(o_dat[10]), + .O(p_1_in[11])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[12]_i_1 + (.I0(i_dat_load[12]), + .I1(i_load), + .I2(o_dat[11]), + .O(p_1_in[12])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[13]_i_1 + (.I0(i_dat_load[13]), + .I1(i_load), + .I2(o_dat[12]), + .O(p_1_in[13])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[14]_i_1 + (.I0(i_dat_load[14]), + .I1(i_load), + .I2(o_dat[13]), + .O(p_1_in[14])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[15]_i_1 + (.I0(i_dat_load[15]), + .I1(i_load), + .I2(o_dat[14]), + .O(p_1_in[15])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[16]_i_1 + (.I0(i_dat_load[16]), + .I1(i_load), + .I2(o_dat[15]), + .O(p_1_in[16])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[17]_i_1 + (.I0(i_dat_load[17]), + .I1(i_load), + .I2(o_dat[16]), + .O(p_1_in[17])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[18]_i_1 + (.I0(i_dat_load[18]), + .I1(i_load), + .I2(o_dat[17]), + .O(p_1_in[18])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[19]_i_1 + (.I0(i_dat_load[19]), + .I1(i_load), + .I2(o_dat[18]), + .O(p_1_in[19])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[1]_i_1 + (.I0(i_dat_load[1]), + .I1(i_load), + .I2(o_dat[0]), + .O(p_1_in[1])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[20]_i_1 + (.I0(i_dat_load[20]), + .I1(i_load), + .I2(o_dat[19]), + .O(p_1_in[20])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[21]_i_1 + (.I0(i_dat_load[21]), + .I1(i_load), + .I2(o_dat[20]), + .O(p_1_in[21])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[22]_i_1 + (.I0(i_dat_load[22]), + .I1(i_load), + .I2(o_dat[21]), + .O(p_1_in[22])); + LUT2 #( + .INIT(4'hE)) + \q_shift_reg[23]_i_1 + (.I0(i_load), + .I1(i_en), + .O(\q_shift_reg[23]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[23]_i_2 + (.I0(i_dat_load[23]), + .I1(i_load), + .I2(o_dat[22]), + .O(p_1_in[23])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[2]_i_1 + (.I0(i_dat_load[2]), + .I1(i_load), + .I2(o_dat[1]), + .O(p_1_in[2])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[3]_i_1 + (.I0(i_dat_load[3]), + .I1(i_load), + .I2(o_dat[2]), + .O(p_1_in[3])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[4]_i_1 + (.I0(i_dat_load[4]), + .I1(i_load), + .I2(o_dat[3]), + .O(p_1_in[4])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[5]_i_1 + (.I0(i_dat_load[5]), + .I1(i_load), + .I2(o_dat[4]), + .O(p_1_in[5])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[6]_i_1 + (.I0(i_dat_load[6]), + .I1(i_load), + .I2(o_dat[5]), + .O(p_1_in[6])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[7]_i_1 + (.I0(i_dat_load[7]), + .I1(i_load), + .I2(o_dat[6]), + .O(p_1_in[7])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[8]_i_1 + (.I0(i_dat_load[8]), + .I1(i_load), + .I2(o_dat[7]), + .O(p_1_in[8])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'hB8)) + \q_shift_reg[9]_i_1 + (.I0(i_dat_load[9]), + .I1(i_load), + .I2(o_dat[8]), + .O(p_1_in[9])); + FDCE \q_shift_reg_reg[0] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[0]), + .Q(o_dat[0])); + FDCE \q_shift_reg_reg[10] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[10]), + .Q(o_dat[10])); + FDCE \q_shift_reg_reg[11] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[11]), + .Q(o_dat[11])); + FDCE \q_shift_reg_reg[12] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[12]), + .Q(o_dat[12])); + FDCE \q_shift_reg_reg[13] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[13]), + .Q(o_dat[13])); + FDCE \q_shift_reg_reg[14] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[14]), + .Q(o_dat[14])); + FDCE \q_shift_reg_reg[15] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[15]), + .Q(o_dat[15])); + FDCE \q_shift_reg_reg[16] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[16]), + .Q(o_dat[16])); + FDCE \q_shift_reg_reg[17] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[17]), + .Q(o_dat[17])); + FDCE \q_shift_reg_reg[18] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[18]), + .Q(o_dat[18])); + FDCE \q_shift_reg_reg[19] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[19]), + .Q(o_dat[19])); + FDCE \q_shift_reg_reg[1] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[1]), + .Q(o_dat[1])); + FDCE \q_shift_reg_reg[20] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[20]), + .Q(o_dat[20])); + FDCE \q_shift_reg_reg[21] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[21]), + .Q(o_dat[21])); + FDCE \q_shift_reg_reg[22] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[22]), + .Q(o_dat[22])); + FDCE \q_shift_reg_reg[23] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[23]), + .Q(o_dat[23])); + FDCE \q_shift_reg_reg[2] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[2]), + .Q(o_dat[2])); + FDCE \q_shift_reg_reg[3] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[3]), + .Q(o_dat[3])); + FDCE \q_shift_reg_reg[4] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[4]), + .Q(o_dat[4])); + FDCE \q_shift_reg_reg[5] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[5]), + .Q(o_dat[5])); + FDCE \q_shift_reg_reg[6] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[6]), + .Q(o_dat[6])); + FDCE \q_shift_reg_reg[7] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[7]), + .Q(o_dat[7])); + FDCE \q_shift_reg_reg[8] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[8]), + .Q(o_dat[8])); + FDCE \q_shift_reg_reg[9] + (.C(i_clk), + .CE(\q_shift_reg[23]_i_1_n_0 ), + .CLR(i_reset), + .D(p_1_in[9]), + .Q(o_dat[9])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_stub.v new file mode 100644 index 0000000..415c9e7 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 11:58:52 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_stub.v +// Design : design_1_reg_dec_24b_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "reg_dec_24b,Vivado 2020.2" *) +module design_1_reg_dec_24b_0_0(i_clk, i_reset, i_load, i_en, i_dat_bit, + i_dat_load, o_dat) +/* synthesis syn_black_box black_box_pad_pin="i_clk,i_reset,i_load,i_en,i_dat_bit,i_dat_load[23:0],o_dat[23:0]" */; + input i_clk; + input i_reset; + input i_load; + input i_en; + input i_dat_bit; + input [23:0]i_dat_load; + output [23:0]o_dat; +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd new file mode 100644 index 0000000..2dbb12a --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd @@ -0,0 +1,101 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:reg_dec_24b:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_reg_dec_24b_0_0 IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_load : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat_bit : IN STD_LOGIC; + i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_reg_dec_24b_0_0; + +ARCHITECTURE design_1_reg_dec_24b_0_0_arch OF design_1_reg_dec_24b_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT reg_dec_24b IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_load : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat_bit : IN STD_LOGIC; + i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT reg_dec_24b; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK"; +BEGIN + U0 : reg_dec_24b + PORT MAP ( + i_clk => i_clk, + i_reset => i_reset, + i_load => i_load, + i_en => i_en, + i_dat_bit => i_dat_bit, + i_dat_load => i_dat_load, + o_dat => o_dat + ); +END design_1_reg_dec_24b_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/synth/design_1_reg_dec_24b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/synth/design_1_reg_dec_24b_0_0.vhd new file mode 100644 index 0000000..b362042 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/synth/design_1_reg_dec_24b_0_0.vhd @@ -0,0 +1,107 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:reg_dec_24b:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_reg_dec_24b_0_0 IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_load : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat_bit : IN STD_LOGIC; + i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_reg_dec_24b_0_0; + +ARCHITECTURE design_1_reg_dec_24b_0_0_arch OF design_1_reg_dec_24b_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT reg_dec_24b IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_load : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat_bit : IN STD_LOGIC; + i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT reg_dec_24b; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "reg_dec_24b,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_reg_dec_24b_0_0_arch : ARCHITECTURE IS "design_1_reg_dec_24b_0_0,reg_dec_24b,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "design_1_reg_dec_24b_0_0,reg_dec_24b,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=reg_dec_24b,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK"; +BEGIN + U0 : reg_dec_24b + PORT MAP ( + i_clk => i_clk, + i_reset => i_reset, + i_load => i_load, + i_en => i_en, + i_dat_bit => i_dat_bit, + i_dat_load => i_dat_load, + o_dat => o_dat + ); +END design_1_reg_dec_24b_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/design_1_reg_dec_24b_fd_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/design_1_reg_dec_24b_fd_0_0.xml new file mode 100644 index 0000000..1c4de0a --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/design_1_reg_dec_24b_fd_0_0.xml @@ -0,0 +1,395 @@ + + + xilinx.com + customized_ip + design_1_reg_dec_24b_fd_0_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + i_clk + + + + + + + CLK + + + i_clk + + + + + + ASSOCIATED_RESET + i_reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + reg_dec_24b_fd + + + outputProductCRC + 9:d3ccf6b8 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_reg_dec_24b_fd_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:d3ccf6b8 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + reg_dec_24b_fd + + + outputProductCRC + 9:565ff38d + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:565ff38d + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_reg_dec_24b_fd_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:565ff38d + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:565ff38d + + + + + + + i_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_load + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_dat_bit + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_dat_load + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_dat + + out + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_reg_dec_24b_fd_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_reg_dec_24b_fd_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_reg_dec_24b_fd_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_reg_dec_24b_fd_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_reg_dec_24b_fd_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_reg_dec_24b_fd_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_reg_dec_24b_fd_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:reg_dec_24b_fd:1.0 + + + Component_Name + design_1_reg_dec_24b_fd_0_0 + + + + + reg_dec_24b_fd_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd new file mode 100644 index 0000000..c8a9b85 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd @@ -0,0 +1,101 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:reg_dec_24b_fd:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_reg_dec_24b_fd_0_0 IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_load : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat_bit : IN STD_LOGIC; + i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_reg_dec_24b_fd_0_0; + +ARCHITECTURE design_1_reg_dec_24b_fd_0_0_arch OF design_1_reg_dec_24b_fd_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT reg_dec_24b_fd IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_load : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat_bit : IN STD_LOGIC; + i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT reg_dec_24b_fd; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK"; +BEGIN + U0 : reg_dec_24b_fd + PORT MAP ( + i_clk => i_clk, + i_reset => i_reset, + i_load => i_load, + i_en => i_en, + i_dat_bit => i_dat_bit, + i_dat_load => i_dat_load, + o_dat => o_dat + ); +END design_1_reg_dec_24b_fd_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/synth/design_1_reg_dec_24b_fd_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/synth/design_1_reg_dec_24b_fd_0_0.vhd new file mode 100644 index 0000000..0015b2e --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/synth/design_1_reg_dec_24b_fd_0_0.vhd @@ -0,0 +1,107 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:reg_dec_24b_fd:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_reg_dec_24b_fd_0_0 IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_load : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat_bit : IN STD_LOGIC; + i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_reg_dec_24b_fd_0_0; + +ARCHITECTURE design_1_reg_dec_24b_fd_0_0_arch OF design_1_reg_dec_24b_fd_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT reg_dec_24b_fd IS + PORT ( + i_clk : IN STD_LOGIC; + i_reset : IN STD_LOGIC; + i_load : IN STD_LOGIC; + i_en : IN STD_LOGIC; + i_dat_bit : IN STD_LOGIC; + i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT reg_dec_24b_fd; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "reg_dec_24b_fd,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_reg_dec_24b_fd_0_0_arch : ARCHITECTURE IS "design_1_reg_dec_24b_fd_0_0,reg_dec_24b_fd,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "design_1_reg_dec_24b_fd_0_0,reg_dec_24b_fd,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=reg_dec_24b_fd,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "module_ref"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK"; +BEGIN + U0 : reg_dec_24b_fd + PORT MAP ( + i_clk => i_clk, + i_reset => i_reset, + i_load => i_load, + i_en => i_en, + i_dat_bit => i_dat_bit, + i_dat_load => i_dat_load, + o_dat => o_dat + ); +END design_1_reg_dec_24b_fd_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0_1/design_1_reg_dec_24b_fd_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0_1/design_1_reg_dec_24b_fd_0_0.xml new file mode 100644 index 0000000..d2c2759 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0_1/design_1_reg_dec_24b_fd_0_0.xml @@ -0,0 +1,243 @@ + + + xilinx.com + customized_ip + design_1_reg_dec_24b_fd_0_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + i_clk + + + + + + + CLK + + + i_clk + + + + + + ASSOCIATED_RESET + i_reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + i_clk + + in + + + std_logic + dummy_view + + + + + + i_reset + + in + + + std_logic + dummy_view + + + + + + i_load + + in + + + std_logic + dummy_view + + + + + + i_en + + in + + + std_logic + dummy_view + + + + + + i_dat_bit + + in + + + std_logic + dummy_view + + + + + + i_dat_load + + in + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_dat + + out + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + + xilinx.com:module_ref:reg_dec_24b_fd:1.0 + + + Component_Name + design_1_reg_dec_24b_fd_0_0 + + + + + reg_dec_24b_fd_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_droite_0/design_1_registre_24bits_droite_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_droite_0/design_1_registre_24bits_droite_0.xml new file mode 100644 index 0000000..6416776 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_droite_0/design_1_registre_24bits_droite_0.xml @@ -0,0 +1,219 @@ + + + xilinx.com + customized_ip + design_1_registre_24bits_droite_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + i_clk + + + + + + + CLK + + + i_clk + + + + + + ASSOCIATED_RESET + i_reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + i_clk + + in + + + std_logic + dummy_view + + + + + + i_reset + + in + + + std_logic + dummy_view + + + + + + i_en + + in + + + std_logic + dummy_view + + + + + + i_dat + + in + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_dat + + out + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + + xilinx.com:module_ref:reg_24b:1.0 + + + Component_Name + design_1_registre_24bits_droite_0 + + + + + reg_24b_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_gauche_0/design_1_registre_24bits_gauche_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_gauche_0/design_1_registre_24bits_gauche_0.xml new file mode 100644 index 0000000..73e2276 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_gauche_0/design_1_registre_24bits_gauche_0.xml @@ -0,0 +1,219 @@ + + + xilinx.com + customized_ip + design_1_registre_24bits_gauche_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + i_clk + + + + + + + CLK + + + i_clk + + + + + + ASSOCIATED_RESET + i_reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + i_clk + + in + + + std_logic + dummy_view + + + + + + i_reset + + in + + + std_logic + dummy_view + + + + + + i_en + + in + + + std_logic + dummy_view + + + + + + i_dat + + in + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_dat + + out + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + + xilinx.com:module_ref:reg_24b:1.0 + + + Component_Name + design_1_registre_24bits_gauche_0 + + + + + reg_24b_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_decalage_24bits_0/design_1_registre_decalage_24bits_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_decalage_24bits_0/design_1_registre_decalage_24bits_0.xml new file mode 100644 index 0000000..3ca96da --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_decalage_24bits_0/design_1_registre_decalage_24bits_0.xml @@ -0,0 +1,243 @@ + + + xilinx.com + customized_ip + design_1_registre_decalage_24bits_0 + 1.0 + + + i_reset + + + + + + + RST + + + i_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + i_clk + + + + + + + CLK + + + i_clk + + + + + + ASSOCIATED_RESET + i_reset + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_clk_100MHz + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + i_clk + + in + + + std_logic + dummy_view + + + + + + i_reset + + in + + + std_logic + dummy_view + + + + + + i_load + + in + + + std_logic + dummy_view + + + + + + i_en + + in + + + std_logic + dummy_view + + + + + + i_dat_bit + + in + + + std_logic + dummy_view + + + + + + i_dat_load + + in + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + o_dat + + out + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + + xilinx.com:module_ref:reg_dec_24b:1.0 + + + Component_Name + design_1_registre_decalage_24bits_0 + + + + + reg_dec_24b_v1_0 + module_ref + 1 + + + + + + + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.dcp new file mode 100644 index 0000000..353b99c Binary files /dev/null and b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.dcp differ diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.xml new file mode 100644 index 0000000..906e901 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.xml @@ -0,0 +1,211 @@ + + + xilinx.com + customized_ip + design_1_sig_fct_3_0_0 + 1.0 + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + sig_fct_3 + + + outputProductCRC + 9:acee340e + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_sig_fct_3_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:acee340e + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + sig_fct_3 + + + outputProductCRC + 9:46469856 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:46469856 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_sig_fct_3_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:46469856 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Tue Jan 16 17:01:55 UTC 2024 + + + outputProductCRC + 9:46469856 + + + + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ech_fct + + out + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_sig_fct_3_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_sig_fct_3_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_sig_fct_3_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_sig_fct_3_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_sig_fct_3_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_sig_fct_3_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_sig_fct_3_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:sig_fct_3:1.0 + + + Component_Name + design_1_sig_fct_3_0_0 + + + + + sig_fct_3_v1_0 + module_ref + 1 + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_sim_netlist.v new file mode 100644 index 0000000..dfd7ce6 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_sim_netlist.v @@ -0,0 +1,110 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 12:01:55 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_sim_netlist.v +// Design : design_1_sig_fct_3_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "design_1_sig_fct_3_0_0,sig_fct_3,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) +(* x_core_info = "sig_fct_3,Vivado 2020.2" *) +(* NotValidForBitStream *) +module design_1_sig_fct_3_0_0 + (i_ech, + o_ech_fct); + input [23:0]i_ech; + output [23:0]o_ech_fct; + + wire [23:0]i_ech; + + assign o_ech_fct[23:0] = i_ech; +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_stub.v new file mode 100644 index 0000000..23d3fb1 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_stub.v @@ -0,0 +1,21 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 12:01:55 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_stub.v +// Design : design_1_sig_fct_3_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "sig_fct_3,Vivado 2020.2" *) +module design_1_sig_fct_3_0_0(i_ech, o_ech_fct) +/* synthesis syn_black_box black_box_pad_pin="i_ech[23:0],o_ech_fct[23:0]" */; + input [23:0]i_ech; + output [23:0]o_ech_fct; +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd new file mode 100644 index 0000000..3a84972 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd @@ -0,0 +1,80 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:sig_fct_3:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_sig_fct_3_0_0 IS + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_sig_fct_3_0_0; + +ARCHITECTURE design_1_sig_fct_3_0_0_arch OF design_1_sig_fct_3_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT sig_fct_3 IS + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT sig_fct_3; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : sig_fct_3 + PORT MAP ( + i_ech => i_ech, + o_ech_fct => o_ech_fct + ); +END design_1_sig_fct_3_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/synth/design_1_sig_fct_3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/synth/design_1_sig_fct_3_0_0.vhd new file mode 100644 index 0000000..6cc4fff --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/synth/design_1_sig_fct_3_0_0.vhd @@ -0,0 +1,86 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:sig_fct_3:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_sig_fct_3_0_0 IS + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_sig_fct_3_0_0; + +ARCHITECTURE design_1_sig_fct_3_0_0_arch OF design_1_sig_fct_3_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT sig_fct_3 IS + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT sig_fct_3; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "sig_fct_3,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_sig_fct_3_0_0_arch : ARCHITECTURE IS "design_1_sig_fct_3_0_0,sig_fct_3,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "design_1_sig_fct_3_0_0,sig_fct_3,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=sig_fct_3,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : sig_fct_3 + PORT MAP ( + i_ech => i_ech, + o_ech_fct => o_ech_fct + ); +END design_1_sig_fct_3_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.dcp new file mode 100644 index 0000000..8363504 Binary files /dev/null and b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.dcp differ diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.xml new file mode 100644 index 0000000..5147b3b --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.xml @@ -0,0 +1,226 @@ + + + xilinx.com + customized_ip + design_1_sig_fct_sat_dure_0_0 + 1.0 + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + sig_fct_sat_dure + + + outputProductCRC + 9:18f92d4c + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_sig_fct_sat_dure_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:18f92d4c + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + sig_fct_sat_dure + + + outputProductCRC + 9:2e91ff3a + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:2e91ff3a + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_sig_fct_sat_dure_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:2e91ff3a + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Tue Jan 16 17:03:16 UTC 2024 + + + outputProductCRC + 9:2e91ff3a + + + + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ech_fct + + out + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + c_ech_u24_max + C Ech U24 Max + 0x7FFFFF + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_sig_fct_sat_dure_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_sig_fct_sat_dure_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_sig_fct_sat_dure_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_sig_fct_sat_dure_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_sig_fct_sat_dure_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_sig_fct_sat_dure_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_sig_fct_sat_dure_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:sig_fct_sat_dure:1.0 + + + c_ech_u24_max + C Ech U24 Max + 0x7FFFFF + + + Component_Name + design_1_sig_fct_sat_dure_0_0 + + + + + sig_fct_sat_dure_v1_0 + module_ref + 1 + + + + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_sim_netlist.v new file mode 100644 index 0000000..a6534d1 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_sim_netlist.v @@ -0,0 +1,896 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 12:03:16 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_sim_netlist.v +// Design : design_1_sig_fct_sat_dure_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "design_1_sig_fct_sat_dure_0_0,sig_fct_sat_dure,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) +(* x_core_info = "sig_fct_sat_dure,Vivado 2020.2" *) +(* NotValidForBitStream *) +module design_1_sig_fct_sat_dure_0_0 + (i_ech, + o_ech_fct); + input [23:0]i_ech; + output [23:0]o_ech_fct; + + wire [23:0]i_ech; + wire [23:0]o_ech_fct; + wire \o_ech_fct[12]_INST_0_i_10_n_0 ; + wire \o_ech_fct[12]_INST_0_i_1_n_0 ; + wire \o_ech_fct[12]_INST_0_i_1_n_1 ; + wire \o_ech_fct[12]_INST_0_i_1_n_2 ; + wire \o_ech_fct[12]_INST_0_i_1_n_3 ; + wire \o_ech_fct[12]_INST_0_i_6_n_0 ; + wire \o_ech_fct[12]_INST_0_i_6_n_1 ; + wire \o_ech_fct[12]_INST_0_i_6_n_2 ; + wire \o_ech_fct[12]_INST_0_i_6_n_3 ; + wire \o_ech_fct[12]_INST_0_i_6_n_4 ; + wire \o_ech_fct[12]_INST_0_i_6_n_5 ; + wire \o_ech_fct[12]_INST_0_i_6_n_6 ; + wire \o_ech_fct[12]_INST_0_i_6_n_7 ; + wire \o_ech_fct[12]_INST_0_i_7_n_0 ; + wire \o_ech_fct[12]_INST_0_i_8_n_0 ; + wire \o_ech_fct[12]_INST_0_i_9_n_0 ; + wire \o_ech_fct[16]_INST_0_i_10_n_0 ; + wire \o_ech_fct[16]_INST_0_i_1_n_0 ; + wire \o_ech_fct[16]_INST_0_i_1_n_1 ; + wire \o_ech_fct[16]_INST_0_i_1_n_2 ; + wire \o_ech_fct[16]_INST_0_i_1_n_3 ; + wire \o_ech_fct[16]_INST_0_i_6_n_0 ; + wire \o_ech_fct[16]_INST_0_i_6_n_1 ; + wire \o_ech_fct[16]_INST_0_i_6_n_2 ; + wire \o_ech_fct[16]_INST_0_i_6_n_3 ; + wire \o_ech_fct[16]_INST_0_i_6_n_4 ; + wire \o_ech_fct[16]_INST_0_i_6_n_5 ; + wire \o_ech_fct[16]_INST_0_i_6_n_6 ; + wire \o_ech_fct[16]_INST_0_i_6_n_7 ; + wire \o_ech_fct[16]_INST_0_i_7_n_0 ; + wire \o_ech_fct[16]_INST_0_i_8_n_0 ; + wire \o_ech_fct[16]_INST_0_i_9_n_0 ; + wire \o_ech_fct[20]_INST_0_i_1_n_0 ; + wire \o_ech_fct[20]_INST_0_i_1_n_1 ; + wire \o_ech_fct[20]_INST_0_i_1_n_2 ; + wire \o_ech_fct[20]_INST_0_i_1_n_3 ; + wire \o_ech_fct[22]_INST_0_i_10_n_0 ; + wire \o_ech_fct[22]_INST_0_i_11_n_0 ; + wire \o_ech_fct[22]_INST_0_i_12_n_0 ; + wire \o_ech_fct[22]_INST_0_i_13_n_0 ; + wire \o_ech_fct[22]_INST_0_i_14_n_0 ; + wire \o_ech_fct[22]_INST_0_i_15_n_0 ; + wire \o_ech_fct[22]_INST_0_i_16_n_0 ; + wire \o_ech_fct[22]_INST_0_i_17_n_0 ; + wire \o_ech_fct[22]_INST_0_i_18_n_0 ; + wire \o_ech_fct[22]_INST_0_i_19_n_0 ; + wire \o_ech_fct[22]_INST_0_i_1_n_0 ; + wire \o_ech_fct[22]_INST_0_i_20_n_0 ; + wire \o_ech_fct[22]_INST_0_i_2_n_0 ; + wire \o_ech_fct[22]_INST_0_i_3_n_0 ; + wire \o_ech_fct[22]_INST_0_i_4_n_2 ; + wire \o_ech_fct[22]_INST_0_i_4_n_3 ; + wire \o_ech_fct[22]_INST_0_i_4_n_5 ; + wire \o_ech_fct[22]_INST_0_i_4_n_6 ; + wire \o_ech_fct[22]_INST_0_i_4_n_7 ; + wire \o_ech_fct[22]_INST_0_i_5_n_0 ; + wire \o_ech_fct[22]_INST_0_i_6_n_0 ; + wire \o_ech_fct[22]_INST_0_i_7_n_0 ; + wire \o_ech_fct[22]_INST_0_i_8_n_0 ; + wire \o_ech_fct[22]_INST_0_i_8_n_1 ; + wire \o_ech_fct[22]_INST_0_i_8_n_2 ; + wire \o_ech_fct[22]_INST_0_i_8_n_3 ; + wire \o_ech_fct[22]_INST_0_i_8_n_4 ; + wire \o_ech_fct[22]_INST_0_i_8_n_5 ; + wire \o_ech_fct[22]_INST_0_i_8_n_6 ; + wire \o_ech_fct[22]_INST_0_i_8_n_7 ; + wire \o_ech_fct[22]_INST_0_i_9_n_0 ; + wire \o_ech_fct[23]_INST_0_i_1_n_1 ; + wire \o_ech_fct[23]_INST_0_i_1_n_3 ; + wire \o_ech_fct[4]_INST_0_i_10_n_0 ; + wire \o_ech_fct[4]_INST_0_i_11_n_0 ; + wire \o_ech_fct[4]_INST_0_i_12_n_0 ; + wire \o_ech_fct[4]_INST_0_i_1_n_0 ; + wire \o_ech_fct[4]_INST_0_i_1_n_1 ; + wire \o_ech_fct[4]_INST_0_i_1_n_2 ; + wire \o_ech_fct[4]_INST_0_i_1_n_3 ; + wire \o_ech_fct[4]_INST_0_i_7_n_0 ; + wire \o_ech_fct[4]_INST_0_i_7_n_1 ; + wire \o_ech_fct[4]_INST_0_i_7_n_2 ; + wire \o_ech_fct[4]_INST_0_i_7_n_3 ; + wire \o_ech_fct[4]_INST_0_i_7_n_4 ; + wire \o_ech_fct[4]_INST_0_i_7_n_5 ; + wire \o_ech_fct[4]_INST_0_i_7_n_6 ; + wire \o_ech_fct[4]_INST_0_i_7_n_7 ; + wire \o_ech_fct[4]_INST_0_i_8_n_0 ; + wire \o_ech_fct[4]_INST_0_i_9_n_0 ; + wire \o_ech_fct[8]_INST_0_i_10_n_0 ; + wire \o_ech_fct[8]_INST_0_i_1_n_0 ; + wire \o_ech_fct[8]_INST_0_i_1_n_1 ; + wire \o_ech_fct[8]_INST_0_i_1_n_2 ; + wire \o_ech_fct[8]_INST_0_i_1_n_3 ; + wire \o_ech_fct[8]_INST_0_i_6_n_0 ; + wire \o_ech_fct[8]_INST_0_i_6_n_1 ; + wire \o_ech_fct[8]_INST_0_i_6_n_2 ; + wire \o_ech_fct[8]_INST_0_i_6_n_3 ; + wire \o_ech_fct[8]_INST_0_i_6_n_4 ; + wire \o_ech_fct[8]_INST_0_i_6_n_5 ; + wire \o_ech_fct[8]_INST_0_i_6_n_6 ; + wire \o_ech_fct[8]_INST_0_i_6_n_7 ; + wire \o_ech_fct[8]_INST_0_i_7_n_0 ; + wire \o_ech_fct[8]_INST_0_i_8_n_0 ; + wire \o_ech_fct[8]_INST_0_i_9_n_0 ; + wire [22:0]p_0_in; + wire [22:1]plusOp; + wire [3:2]\NLW_o_ech_fct[22]_INST_0_i_4_CO_UNCONNECTED ; + wire [3:3]\NLW_o_ech_fct[22]_INST_0_i_4_O_UNCONNECTED ; + wire [3:1]\NLW_o_ech_fct[23]_INST_0_i_1_CO_UNCONNECTED ; + wire [3:2]\NLW_o_ech_fct[23]_INST_0_i_1_O_UNCONNECTED ; + + LUT2 #( + .INIT(4'hE)) + \o_ech_fct[0]_INST_0 + (.I0(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I1(i_ech[0]), + .O(o_ech_fct[0])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[10]_INST_0 + (.I0(plusOp[10]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[10]), + .O(o_ech_fct[10])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[11]_INST_0 + (.I0(plusOp[11]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[11]), + .O(o_ech_fct[11])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[12]_INST_0 + (.I0(plusOp[12]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[12]), + .O(o_ech_fct[12])); + CARRY4 \o_ech_fct[12]_INST_0_i_1 + (.CI(\o_ech_fct[8]_INST_0_i_1_n_0 ), + .CO({\o_ech_fct[12]_INST_0_i_1_n_0 ,\o_ech_fct[12]_INST_0_i_1_n_1 ,\o_ech_fct[12]_INST_0_i_1_n_2 ,\o_ech_fct[12]_INST_0_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(plusOp[12:9]), + .S(p_0_in[12:9])); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[12]_INST_0_i_10 + (.I0(i_ech[9]), + .O(\o_ech_fct[12]_INST_0_i_10_n_0 )); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[12]_INST_0_i_2 + (.I0(\o_ech_fct[12]_INST_0_i_6_n_4 ), + .I1(i_ech[23]), + .I2(i_ech[12]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[12])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[12]_INST_0_i_3 + (.I0(\o_ech_fct[12]_INST_0_i_6_n_5 ), + .I1(i_ech[23]), + .I2(i_ech[11]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[11])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[12]_INST_0_i_4 + (.I0(\o_ech_fct[12]_INST_0_i_6_n_6 ), + .I1(i_ech[23]), + .I2(i_ech[10]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[10])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[12]_INST_0_i_5 + (.I0(\o_ech_fct[12]_INST_0_i_6_n_7 ), + .I1(i_ech[23]), + .I2(i_ech[9]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[9])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \o_ech_fct[12]_INST_0_i_6 + (.CI(\o_ech_fct[8]_INST_0_i_6_n_0 ), + .CO({\o_ech_fct[12]_INST_0_i_6_n_0 ,\o_ech_fct[12]_INST_0_i_6_n_1 ,\o_ech_fct[12]_INST_0_i_6_n_2 ,\o_ech_fct[12]_INST_0_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\o_ech_fct[12]_INST_0_i_6_n_4 ,\o_ech_fct[12]_INST_0_i_6_n_5 ,\o_ech_fct[12]_INST_0_i_6_n_6 ,\o_ech_fct[12]_INST_0_i_6_n_7 }), + .S({\o_ech_fct[12]_INST_0_i_7_n_0 ,\o_ech_fct[12]_INST_0_i_8_n_0 ,\o_ech_fct[12]_INST_0_i_9_n_0 ,\o_ech_fct[12]_INST_0_i_10_n_0 })); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[12]_INST_0_i_7 + (.I0(i_ech[12]), + .O(\o_ech_fct[12]_INST_0_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[12]_INST_0_i_8 + (.I0(i_ech[11]), + .O(\o_ech_fct[12]_INST_0_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[12]_INST_0_i_9 + (.I0(i_ech[10]), + .O(\o_ech_fct[12]_INST_0_i_9_n_0 )); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[13]_INST_0 + (.I0(plusOp[13]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[13]), + .O(o_ech_fct[13])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[14]_INST_0 + (.I0(plusOp[14]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[14]), + .O(o_ech_fct[14])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[15]_INST_0 + (.I0(plusOp[15]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[15]), + .O(o_ech_fct[15])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[16]_INST_0 + (.I0(plusOp[16]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[16]), + .O(o_ech_fct[16])); + CARRY4 \o_ech_fct[16]_INST_0_i_1 + (.CI(\o_ech_fct[12]_INST_0_i_1_n_0 ), + .CO({\o_ech_fct[16]_INST_0_i_1_n_0 ,\o_ech_fct[16]_INST_0_i_1_n_1 ,\o_ech_fct[16]_INST_0_i_1_n_2 ,\o_ech_fct[16]_INST_0_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(plusOp[16:13]), + .S(p_0_in[16:13])); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[16]_INST_0_i_10 + (.I0(i_ech[13]), + .O(\o_ech_fct[16]_INST_0_i_10_n_0 )); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[16]_INST_0_i_2 + (.I0(\o_ech_fct[16]_INST_0_i_6_n_4 ), + .I1(i_ech[23]), + .I2(i_ech[16]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[16])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[16]_INST_0_i_3 + (.I0(\o_ech_fct[16]_INST_0_i_6_n_5 ), + .I1(i_ech[23]), + .I2(i_ech[15]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[15])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[16]_INST_0_i_4 + (.I0(\o_ech_fct[16]_INST_0_i_6_n_6 ), + .I1(i_ech[23]), + .I2(i_ech[14]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[14])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[16]_INST_0_i_5 + (.I0(\o_ech_fct[16]_INST_0_i_6_n_7 ), + .I1(i_ech[23]), + .I2(i_ech[13]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[13])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \o_ech_fct[16]_INST_0_i_6 + (.CI(\o_ech_fct[12]_INST_0_i_6_n_0 ), + .CO({\o_ech_fct[16]_INST_0_i_6_n_0 ,\o_ech_fct[16]_INST_0_i_6_n_1 ,\o_ech_fct[16]_INST_0_i_6_n_2 ,\o_ech_fct[16]_INST_0_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\o_ech_fct[16]_INST_0_i_6_n_4 ,\o_ech_fct[16]_INST_0_i_6_n_5 ,\o_ech_fct[16]_INST_0_i_6_n_6 ,\o_ech_fct[16]_INST_0_i_6_n_7 }), + .S({\o_ech_fct[16]_INST_0_i_7_n_0 ,\o_ech_fct[16]_INST_0_i_8_n_0 ,\o_ech_fct[16]_INST_0_i_9_n_0 ,\o_ech_fct[16]_INST_0_i_10_n_0 })); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[16]_INST_0_i_7 + (.I0(i_ech[16]), + .O(\o_ech_fct[16]_INST_0_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[16]_INST_0_i_8 + (.I0(i_ech[15]), + .O(\o_ech_fct[16]_INST_0_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[16]_INST_0_i_9 + (.I0(i_ech[14]), + .O(\o_ech_fct[16]_INST_0_i_9_n_0 )); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[17]_INST_0 + (.I0(plusOp[17]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[17]), + .O(o_ech_fct[17])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[18]_INST_0 + (.I0(plusOp[18]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[18]), + .O(o_ech_fct[18])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[19]_INST_0 + (.I0(plusOp[19]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[19]), + .O(o_ech_fct[19])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[1]_INST_0 + (.I0(plusOp[1]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[1]), + .O(o_ech_fct[1])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[20]_INST_0 + (.I0(plusOp[20]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[20]), + .O(o_ech_fct[20])); + CARRY4 \o_ech_fct[20]_INST_0_i_1 + (.CI(\o_ech_fct[16]_INST_0_i_1_n_0 ), + .CO({\o_ech_fct[20]_INST_0_i_1_n_0 ,\o_ech_fct[20]_INST_0_i_1_n_1 ,\o_ech_fct[20]_INST_0_i_1_n_2 ,\o_ech_fct[20]_INST_0_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(plusOp[20:17]), + .S(p_0_in[20:17])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[20]_INST_0_i_2 + (.I0(\o_ech_fct[22]_INST_0_i_8_n_4 ), + .I1(i_ech[23]), + .I2(i_ech[20]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[20])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[20]_INST_0_i_3 + (.I0(\o_ech_fct[22]_INST_0_i_8_n_5 ), + .I1(i_ech[23]), + .I2(i_ech[19]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[19])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[20]_INST_0_i_4 + (.I0(\o_ech_fct[22]_INST_0_i_8_n_6 ), + .I1(i_ech[23]), + .I2(i_ech[18]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[18])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[20]_INST_0_i_5 + (.I0(\o_ech_fct[22]_INST_0_i_8_n_7 ), + .I1(i_ech[23]), + .I2(i_ech[17]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[17])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[21]_INST_0 + (.I0(plusOp[21]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[21]), + .O(o_ech_fct[21])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[22]_INST_0 + (.I0(plusOp[22]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[22]), + .O(o_ech_fct[22])); + LUT6 #( + .INIT(64'hF000FFFFF000E000)) + \o_ech_fct[22]_INST_0_i_1 + (.I0(\o_ech_fct[22]_INST_0_i_2_n_0 ), + .I1(\o_ech_fct[22]_INST_0_i_3_n_0 ), + .I2(\o_ech_fct[22]_INST_0_i_4_n_5 ), + .I3(i_ech[23]), + .I4(\o_ech_fct[22]_INST_0_i_5_n_0 ), + .I5(\o_ech_fct[22]_INST_0_i_6_n_0 ), + .O(\o_ech_fct[22]_INST_0_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[22]_INST_0_i_10 + (.I0(i_ech[22]), + .O(\o_ech_fct[22]_INST_0_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[22]_INST_0_i_11 + (.I0(i_ech[21]), + .O(\o_ech_fct[22]_INST_0_i_11_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \o_ech_fct[22]_INST_0_i_12 + (.I0(i_ech[12]), + .I1(i_ech[13]), + .I2(i_ech[14]), + .I3(i_ech[15]), + .O(\o_ech_fct[22]_INST_0_i_12_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hFFFE)) + \o_ech_fct[22]_INST_0_i_13 + (.I0(i_ech[16]), + .I1(i_ech[17]), + .I2(i_ech[18]), + .I3(i_ech[19]), + .O(\o_ech_fct[22]_INST_0_i_13_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \o_ech_fct[22]_INST_0_i_14 + (.I0(i_ech[4]), + .I1(i_ech[5]), + .I2(i_ech[6]), + .I3(i_ech[7]), + .O(\o_ech_fct[22]_INST_0_i_14_n_0 )); + LUT4 #( + .INIT(16'h0001)) + \o_ech_fct[22]_INST_0_i_15 + (.I0(i_ech[1]), + .I1(i_ech[0]), + .I2(i_ech[3]), + .I3(i_ech[2]), + .O(\o_ech_fct[22]_INST_0_i_15_n_0 )); + LUT2 #( + .INIT(4'h1)) + \o_ech_fct[22]_INST_0_i_16 + (.I0(i_ech[20]), + .I1(i_ech[21]), + .O(\o_ech_fct[22]_INST_0_i_16_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[22]_INST_0_i_17 + (.I0(i_ech[20]), + .O(\o_ech_fct[22]_INST_0_i_17_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[22]_INST_0_i_18 + (.I0(i_ech[19]), + .O(\o_ech_fct[22]_INST_0_i_18_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[22]_INST_0_i_19 + (.I0(i_ech[18]), + .O(\o_ech_fct[22]_INST_0_i_19_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFFFF)) + \o_ech_fct[22]_INST_0_i_2 + (.I0(i_ech[2]), + .I1(i_ech[1]), + .I2(i_ech[3]), + .I3(i_ech[22]), + .I4(i_ech[23]), + .I5(\o_ech_fct[22]_INST_0_i_7_n_0 ), + .O(\o_ech_fct[22]_INST_0_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[22]_INST_0_i_20 + (.I0(i_ech[17]), + .O(\o_ech_fct[22]_INST_0_i_20_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hFFFFFFFE)) + \o_ech_fct[22]_INST_0_i_3 + (.I0(i_ech[0]), + .I1(i_ech[19]), + .I2(i_ech[18]), + .I3(i_ech[17]), + .I4(i_ech[16]), + .O(\o_ech_fct[22]_INST_0_i_3_n_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \o_ech_fct[22]_INST_0_i_4 + (.CI(\o_ech_fct[22]_INST_0_i_8_n_0 ), + .CO({\NLW_o_ech_fct[22]_INST_0_i_4_CO_UNCONNECTED [3:2],\o_ech_fct[22]_INST_0_i_4_n_2 ,\o_ech_fct[22]_INST_0_i_4_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_o_ech_fct[22]_INST_0_i_4_O_UNCONNECTED [3],\o_ech_fct[22]_INST_0_i_4_n_5 ,\o_ech_fct[22]_INST_0_i_4_n_6 ,\o_ech_fct[22]_INST_0_i_4_n_7 }), + .S({1'b0,\o_ech_fct[22]_INST_0_i_9_n_0 ,\o_ech_fct[22]_INST_0_i_10_n_0 ,\o_ech_fct[22]_INST_0_i_11_n_0 })); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \o_ech_fct[22]_INST_0_i_5 + (.I0(i_ech[11]), + .I1(i_ech[10]), + .I2(i_ech[9]), + .I3(i_ech[8]), + .I4(\o_ech_fct[22]_INST_0_i_12_n_0 ), + .O(\o_ech_fct[22]_INST_0_i_5_n_0 )); + LUT6 #( + .INIT(64'h0010000000000000)) + \o_ech_fct[22]_INST_0_i_6 + (.I0(\o_ech_fct[22]_INST_0_i_13_n_0 ), + .I1(\o_ech_fct[22]_INST_0_i_14_n_0 ), + .I2(\o_ech_fct[22]_INST_0_i_15_n_0 ), + .I3(i_ech[22]), + .I4(i_ech[23]), + .I5(\o_ech_fct[22]_INST_0_i_16_n_0 ), + .O(\o_ech_fct[22]_INST_0_i_6_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \o_ech_fct[22]_INST_0_i_7 + (.I0(i_ech[7]), + .I1(i_ech[6]), + .I2(i_ech[5]), + .I3(i_ech[4]), + .I4(i_ech[21]), + .I5(i_ech[20]), + .O(\o_ech_fct[22]_INST_0_i_7_n_0 )); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \o_ech_fct[22]_INST_0_i_8 + (.CI(\o_ech_fct[16]_INST_0_i_6_n_0 ), + .CO({\o_ech_fct[22]_INST_0_i_8_n_0 ,\o_ech_fct[22]_INST_0_i_8_n_1 ,\o_ech_fct[22]_INST_0_i_8_n_2 ,\o_ech_fct[22]_INST_0_i_8_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\o_ech_fct[22]_INST_0_i_8_n_4 ,\o_ech_fct[22]_INST_0_i_8_n_5 ,\o_ech_fct[22]_INST_0_i_8_n_6 ,\o_ech_fct[22]_INST_0_i_8_n_7 }), + .S({\o_ech_fct[22]_INST_0_i_17_n_0 ,\o_ech_fct[22]_INST_0_i_18_n_0 ,\o_ech_fct[22]_INST_0_i_19_n_0 ,\o_ech_fct[22]_INST_0_i_20_n_0 })); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[22]_INST_0_i_9 + (.I0(i_ech[23]), + .O(\o_ech_fct[22]_INST_0_i_9_n_0 )); + LUT2 #( + .INIT(4'h2)) + \o_ech_fct[23]_INST_0 + (.I0(i_ech[23]), + .I1(\o_ech_fct[23]_INST_0_i_1_n_1 ), + .O(o_ech_fct[23])); + CARRY4 \o_ech_fct[23]_INST_0_i_1 + (.CI(\o_ech_fct[20]_INST_0_i_1_n_0 ), + .CO({\NLW_o_ech_fct[23]_INST_0_i_1_CO_UNCONNECTED [3],\o_ech_fct[23]_INST_0_i_1_n_1 ,\NLW_o_ech_fct[23]_INST_0_i_1_CO_UNCONNECTED [1],\o_ech_fct[23]_INST_0_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_o_ech_fct[23]_INST_0_i_1_O_UNCONNECTED [3:2],plusOp[22:21]}), + .S({1'b0,1'b1,p_0_in[22:21]})); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[23]_INST_0_i_2 + (.I0(\o_ech_fct[22]_INST_0_i_4_n_6 ), + .I1(i_ech[23]), + .I2(i_ech[22]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[22])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[23]_INST_0_i_3 + (.I0(\o_ech_fct[22]_INST_0_i_4_n_7 ), + .I1(i_ech[23]), + .I2(i_ech[21]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[21])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[2]_INST_0 + (.I0(plusOp[2]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[2]), + .O(o_ech_fct[2])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[3]_INST_0 + (.I0(plusOp[3]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[3]), + .O(o_ech_fct[3])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[4]_INST_0 + (.I0(plusOp[4]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[4]), + .O(o_ech_fct[4])); + CARRY4 \o_ech_fct[4]_INST_0_i_1 + (.CI(1'b0), + .CO({\o_ech_fct[4]_INST_0_i_1_n_0 ,\o_ech_fct[4]_INST_0_i_1_n_1 ,\o_ech_fct[4]_INST_0_i_1_n_2 ,\o_ech_fct[4]_INST_0_i_1_n_3 }), + .CYINIT(p_0_in[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(plusOp[4:1]), + .S(p_0_in[4:1])); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[4]_INST_0_i_10 + (.I0(i_ech[3]), + .O(\o_ech_fct[4]_INST_0_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[4]_INST_0_i_11 + (.I0(i_ech[2]), + .O(\o_ech_fct[4]_INST_0_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[4]_INST_0_i_12 + (.I0(i_ech[1]), + .O(\o_ech_fct[4]_INST_0_i_12_n_0 )); + LUT2 #( + .INIT(4'h1)) + \o_ech_fct[4]_INST_0_i_2 + (.I0(i_ech[0]), + .I1(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[0])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[4]_INST_0_i_3 + (.I0(\o_ech_fct[4]_INST_0_i_7_n_4 ), + .I1(i_ech[23]), + .I2(i_ech[4]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[4])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[4]_INST_0_i_4 + (.I0(\o_ech_fct[4]_INST_0_i_7_n_5 ), + .I1(i_ech[23]), + .I2(i_ech[3]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[3])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[4]_INST_0_i_5 + (.I0(\o_ech_fct[4]_INST_0_i_7_n_6 ), + .I1(i_ech[23]), + .I2(i_ech[2]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[2])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[4]_INST_0_i_6 + (.I0(\o_ech_fct[4]_INST_0_i_7_n_7 ), + .I1(i_ech[23]), + .I2(i_ech[1]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[1])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \o_ech_fct[4]_INST_0_i_7 + (.CI(1'b0), + .CO({\o_ech_fct[4]_INST_0_i_7_n_0 ,\o_ech_fct[4]_INST_0_i_7_n_1 ,\o_ech_fct[4]_INST_0_i_7_n_2 ,\o_ech_fct[4]_INST_0_i_7_n_3 }), + .CYINIT(\o_ech_fct[4]_INST_0_i_8_n_0 ), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\o_ech_fct[4]_INST_0_i_7_n_4 ,\o_ech_fct[4]_INST_0_i_7_n_5 ,\o_ech_fct[4]_INST_0_i_7_n_6 ,\o_ech_fct[4]_INST_0_i_7_n_7 }), + .S({\o_ech_fct[4]_INST_0_i_9_n_0 ,\o_ech_fct[4]_INST_0_i_10_n_0 ,\o_ech_fct[4]_INST_0_i_11_n_0 ,\o_ech_fct[4]_INST_0_i_12_n_0 })); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[4]_INST_0_i_8 + (.I0(i_ech[0]), + .O(\o_ech_fct[4]_INST_0_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[4]_INST_0_i_9 + (.I0(i_ech[4]), + .O(\o_ech_fct[4]_INST_0_i_9_n_0 )); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[5]_INST_0 + (.I0(plusOp[5]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[5]), + .O(o_ech_fct[5])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[6]_INST_0 + (.I0(plusOp[6]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[6]), + .O(o_ech_fct[6])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[7]_INST_0 + (.I0(plusOp[7]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[7]), + .O(o_ech_fct[7])); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[8]_INST_0 + (.I0(plusOp[8]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[8]), + .O(o_ech_fct[8])); + CARRY4 \o_ech_fct[8]_INST_0_i_1 + (.CI(\o_ech_fct[4]_INST_0_i_1_n_0 ), + .CO({\o_ech_fct[8]_INST_0_i_1_n_0 ,\o_ech_fct[8]_INST_0_i_1_n_1 ,\o_ech_fct[8]_INST_0_i_1_n_2 ,\o_ech_fct[8]_INST_0_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(plusOp[8:5]), + .S(p_0_in[8:5])); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[8]_INST_0_i_10 + (.I0(i_ech[5]), + .O(\o_ech_fct[8]_INST_0_i_10_n_0 )); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[8]_INST_0_i_2 + (.I0(\o_ech_fct[8]_INST_0_i_6_n_4 ), + .I1(i_ech[23]), + .I2(i_ech[8]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[8])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[8]_INST_0_i_3 + (.I0(\o_ech_fct[8]_INST_0_i_6_n_5 ), + .I1(i_ech[23]), + .I2(i_ech[7]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[7])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[8]_INST_0_i_4 + (.I0(\o_ech_fct[8]_INST_0_i_6_n_6 ), + .I1(i_ech[23]), + .I2(i_ech[6]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[6])); + LUT4 #( + .INIT(16'h0047)) + \o_ech_fct[8]_INST_0_i_5 + (.I0(\o_ech_fct[8]_INST_0_i_6_n_7 ), + .I1(i_ech[23]), + .I2(i_ech[5]), + .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .O(p_0_in[5])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \o_ech_fct[8]_INST_0_i_6 + (.CI(\o_ech_fct[4]_INST_0_i_7_n_0 ), + .CO({\o_ech_fct[8]_INST_0_i_6_n_0 ,\o_ech_fct[8]_INST_0_i_6_n_1 ,\o_ech_fct[8]_INST_0_i_6_n_2 ,\o_ech_fct[8]_INST_0_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\o_ech_fct[8]_INST_0_i_6_n_4 ,\o_ech_fct[8]_INST_0_i_6_n_5 ,\o_ech_fct[8]_INST_0_i_6_n_6 ,\o_ech_fct[8]_INST_0_i_6_n_7 }), + .S({\o_ech_fct[8]_INST_0_i_7_n_0 ,\o_ech_fct[8]_INST_0_i_8_n_0 ,\o_ech_fct[8]_INST_0_i_9_n_0 ,\o_ech_fct[8]_INST_0_i_10_n_0 })); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[8]_INST_0_i_7 + (.I0(i_ech[8]), + .O(\o_ech_fct[8]_INST_0_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[8]_INST_0_i_8 + (.I0(i_ech[7]), + .O(\o_ech_fct[8]_INST_0_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \o_ech_fct[8]_INST_0_i_9 + (.I0(i_ech[6]), + .O(\o_ech_fct[8]_INST_0_i_9_n_0 )); + LUT4 #( + .INIT(16'hBBB8)) + \o_ech_fct[9]_INST_0 + (.I0(plusOp[9]), + .I1(i_ech[23]), + .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ), + .I3(i_ech[9]), + .O(o_ech_fct[9])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_stub.v new file mode 100644 index 0000000..55b1bdc --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_stub.v @@ -0,0 +1,21 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Tue Jan 16 12:03:16 2024 +// Host : gegi-3014-bmwin running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_stub.v +// Design : design_1_sig_fct_sat_dure_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "sig_fct_sat_dure,Vivado 2020.2" *) +module design_1_sig_fct_sat_dure_0_0(i_ech, o_ech_fct) +/* synthesis syn_black_box black_box_pad_pin="i_ech[23:0],o_ech_fct[23:0]" */; + input [23:0]i_ech; + output [23:0]o_ech_fct; +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd new file mode 100644 index 0000000..27c63d5 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd @@ -0,0 +1,86 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_sig_fct_sat_dure_0_0 IS + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_sig_fct_sat_dure_0_0; + +ARCHITECTURE design_1_sig_fct_sat_dure_0_0_arch OF design_1_sig_fct_sat_dure_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT sig_fct_sat_dure IS + GENERIC ( + c_ech_u24_max : UNSIGNED(23 DOWNTO 0) + ); + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT sig_fct_sat_dure; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : sig_fct_sat_dure + GENERIC MAP ( + c_ech_u24_max => X"7FFFFF" + ) + PORT MAP ( + i_ech => i_ech, + o_ech_fct => o_ech_fct + ); +END design_1_sig_fct_sat_dure_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/synth/design_1_sig_fct_sat_dure_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/synth/design_1_sig_fct_sat_dure_0_0.vhd new file mode 100644 index 0000000..9b42275 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/synth/design_1_sig_fct_sat_dure_0_0.vhd @@ -0,0 +1,92 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_sig_fct_sat_dure_0_0 IS + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_sig_fct_sat_dure_0_0; + +ARCHITECTURE design_1_sig_fct_sat_dure_0_0_arch OF design_1_sig_fct_sat_dure_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT sig_fct_sat_dure IS + GENERIC ( + c_ech_u24_max : UNSIGNED(23 DOWNTO 0) + ); + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT sig_fct_sat_dure; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "sig_fct_sat_dure,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_sig_fct_sat_dure_0_0_arch : ARCHITECTURE IS "design_1_sig_fct_sat_dure_0_0,sig_fct_sat_dure,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "design_1_sig_fct_sat_dure_0_0,sig_fct_sat_dure,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=sig_fct_sat_dure,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,c_ech_u24_max=0x7FFFFF}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : sig_fct_sat_dure + GENERIC MAP ( + c_ech_u24_max => X"7FFFFF" + ) + PORT MAP ( + i_ech => i_ech, + o_ech_fct => o_ech_fct + ); +END design_1_sig_fct_sat_dure_0_0_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/design_1_sig_fct_sat_dure_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/design_1_sig_fct_sat_dure_0_1.xml new file mode 100644 index 0000000..07731a7 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/design_1_sig_fct_sat_dure_0_1.xml @@ -0,0 +1,219 @@ + + + xilinx.com + customized_ip + design_1_sig_fct_sat_dure_0_1 + 1.0 + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + sig_fct_sat_dure + + + outputProductCRC + 9:9a3245c3 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_sig_fct_sat_dure_0_1 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:9a3245c3 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + sig_fct_sat_dure + + + outputProductCRC + 9:168f8b75 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:168f8b75 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_sig_fct_sat_dure_0_1 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:168f8b75 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:168f8b75 + + + + + + + i_ech + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ech_fct + + out + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + c_ech_u24_max + C Ech U24 Max + 0x1FFFFF + + + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_sig_fct_sat_dure_0_1.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_sig_fct_sat_dure_0_1.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_sig_fct_sat_dure_0_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_sig_fct_sat_dure_0_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_sig_fct_sat_dure_0_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_sig_fct_sat_dure_0_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_sig_fct_sat_dure_0_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:sig_fct_sat_dure:1.0 + + + c_ech_u24_max + C Ech U24 Max + 0x1FFFFF + + + Component_Name + design_1_sig_fct_sat_dure_0_1 + + + + + sig_fct_sat_dure_v1_0 + module_ref + 1 + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd new file mode 100644 index 0000000..b557a37 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd @@ -0,0 +1,86 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_sig_fct_sat_dure_0_1 IS + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_sig_fct_sat_dure_0_1; + +ARCHITECTURE design_1_sig_fct_sat_dure_0_1_arch OF design_1_sig_fct_sat_dure_0_1 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "yes"; + COMPONENT sig_fct_sat_dure IS + GENERIC ( + c_ech_u24_max : UNSIGNED(23 DOWNTO 0) + ); + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT sig_fct_sat_dure; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : sig_fct_sat_dure + GENERIC MAP ( + c_ech_u24_max => X"1FFFFF" + ) + PORT MAP ( + i_ech => i_ech, + o_ech_fct => o_ech_fct + ); +END design_1_sig_fct_sat_dure_0_1_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/synth/design_1_sig_fct_sat_dure_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/synth/design_1_sig_fct_sat_dure_0_1.vhd new file mode 100644 index 0000000..51b2616 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/synth/design_1_sig_fct_sat_dure_0_1.vhd @@ -0,0 +1,92 @@ +-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY design_1_sig_fct_sat_dure_0_1 IS + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END design_1_sig_fct_sat_dure_0_1; + +ARCHITECTURE design_1_sig_fct_sat_dure_0_1_arch OF design_1_sig_fct_sat_dure_0_1 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "yes"; + COMPONENT sig_fct_sat_dure IS + GENERIC ( + c_ech_u24_max : UNSIGNED(23 DOWNTO 0) + ); + PORT ( + i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + END COMPONENT sig_fct_sat_dure; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "sig_fct_sat_dure,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_sig_fct_sat_dure_0_1_arch : ARCHITECTURE IS "design_1_sig_fct_sat_dure_0_1,sig_fct_sat_dure,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "design_1_sig_fct_sat_dure_0_1,sig_fct_sat_dure,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=sig_fct_sat_dure,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,c_ech_u24_max=0x1FFFFF}"; + ATTRIBUTE IP_DEFINITION_SOURCE : STRING; + ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "module_ref"; +BEGIN + U0 : sig_fct_sat_dure + GENERIC MAP ( + c_ech_u24_max => X"1FFFFF" + ) + PORT MAP ( + i_ech => i_ech, + o_ech_fct => o_ech_fct + ); +END design_1_sig_fct_sat_dure_0_1_arch; diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xml new file mode 100644 index 0000000..370f24f --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xml @@ -0,0 +1,320 @@ + + + xilinx.com + customized_ip + design_1_util_vector_logic_0_0 + 1.0 + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + util_vector_logic_v2_0_1_util_vector_logic + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:f5f3e7cb + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + design_1_util_vector_logic_0_0 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:f5f3e7cb + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + util_vector_logic_v2_0_1_util_vector_logic + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:0c521749 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:0c521749 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + design_1_util_vector_logic_0_0 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:0c521749 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + outputProductCRC + 9:0c521749 + + + + + + + Op1 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + Op2 + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + Res + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + C_OPERATION + C Operation + or + + + C_SIZE + C Size + 1 + + + + + + choice_list_e94027ef + and + or + xor + not + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v + verilogSource + USED_IN_ipstatic + util_vector_logic_v2_0_1 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/design_1_util_vector_logic_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_verilogsynthesis_view_fileset + + ../../ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v + verilogSource + util_vector_logic_v2_0_1 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/design_1_util_vector_logic_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_util_vector_logic_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_util_vector_logic_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_util_vector_logic_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_util_vector_logic_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_util_vector_logic_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + Performs bitwise logic operations on two n-bit inputs to produce a single n-bit output + + + Component_Name + design_1_util_vector_logic_0_0 + + + C_SIZE + C_SIZE + 1 + + + C_OPERATION + C_OPERATION + or + + + LOGO_FILE + data/sym_orgate.png + + + + false + + + + + + + + Utility Vector Logic + 1 + + + + + + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v new file mode 100644 index 0000000..c3f6299 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v @@ -0,0 +1,74 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:util_vector_logic:2.0 +// IP Revision: 1 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_util_vector_logic_0_0 ( + Op1, + Op2, + Res +); + +input wire [0 : 0] Op1; +input wire [0 : 0] Op2; +output wire [0 : 0] Res; + + util_vector_logic_v2_0_1_util_vector_logic #( + .C_OPERATION("or"), + .C_SIZE(1) + ) inst ( + .Op1(Op1), + .Op2(Op2), + .Res(Res) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/synth/design_1_util_vector_logic_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/synth/design_1_util_vector_logic_0_0.v new file mode 100644 index 0000000..7d09a63 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/synth/design_1_util_vector_logic_0_0.v @@ -0,0 +1,75 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:util_vector_logic:2.0 +// IP Revision: 1 + +(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2020.2" *) +(* CHECK_LICENSE_TYPE = "design_1_util_vector_logic_0_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *) +(* CORE_GENERATION_INFO = "design_1_util_vector_logic_0_0,util_vector_logic_v2_0_1_util_vector_logic,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=or,C_SIZE=1}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_util_vector_logic_0_0 ( + Op1, + Op2, + Res +); + +input wire [0 : 0] Op1; +input wire [0 : 0] Op2; +output wire [0 : 0] Res; + + util_vector_logic_v2_0_1_util_vector_logic #( + .C_OPERATION("or"), + .C_SIZE(1) + ) inst ( + .Op1(Op1), + .Op2(Op2), + .Res(Res) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0_1/design_1_util_vector_logic_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0_1/design_1_util_vector_logic_0_0.xml new file mode 100644 index 0000000..d5d682f --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0_1/design_1_util_vector_logic_0_0.xml @@ -0,0 +1,138 @@ + + + xilinx.com + customized_ip + design_1_util_vector_logic_0_0 + 1.0 + + + + Op1 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Op2 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + true + + + + + + Res + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + C_OPERATION + C Operation + or + + + C_SIZE + C Size + 1 + + + + + + choice_list_e94027ef + and + or + xor + not + + + Performs bitwise logic operations on two n-bit inputs to produce a single n-bit output + + + Component_Name + design_1_util_vector_logic_0_0 + + + C_SIZE + C_SIZE + 1 + + + C_OPERATION + C_OPERATION + or + + + LOGO_FILE + data/sym_orgate.png + + + + false + + + + + + + + Utility Vector Logic + 1 + + + + + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xml new file mode 100644 index 0000000..6c0d417 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xml @@ -0,0 +1,5065 @@ + + + xilinx.com + customized_ip + design_1_xlconcat_0_0 + 1.0 + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + 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of Ports + 2 + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + xlconcat_v2_1_4 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/design_1_xlconcat_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_verilogsynthesis_view_fileset + + ../../ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v + verilogSource + xlconcat_v2_1_4 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/design_1_xlconcat_0_0.v + verilogSource + xil_defaultlib + + + + Concatenates up to 128 ports into a single port + + + Component_Name + design_1_xlconcat_0_0 + + + NUM_PORTS + Number of Ports + 2 + + + IN0_WIDTH + In0 Width + 1 + + + IN1_WIDTH + In1 Width + 1 + + + IN2_WIDTH + In2 Width + 1 + + + IN3_WIDTH + In3 Width + 1 + + + IN4_WIDTH + In4 Width + 1 + + + IN5_WIDTH + In5 Width + 1 + + + IN6_WIDTH + In6 Width + 1 + + + IN7_WIDTH + In7 Width + 1 + + + IN8_WIDTH + In8 Width + 1 + + + IN9_WIDTH + In9 Width + 1 + + + IN10_WIDTH + In10 Width + 1 + + + IN11_WIDTH + In11 Width + 1 + + + IN12_WIDTH + In12 Width + 1 + + + IN13_WIDTH + In13 Width + 1 + + + IN14_WIDTH + In14 Width + 1 + + + IN15_WIDTH + In15 Width + 1 + + + IN16_WIDTH + In16 Width + 1 + + + IN17_WIDTH + In17 Width + 1 + + + IN18_WIDTH + In18 Width + 1 + + + IN19_WIDTH + In19 Width + 1 + + + IN20_WIDTH + In20 Width + 1 + + + IN21_WIDTH + In21 Width + 1 + + + IN22_WIDTH + In22 Width + 1 + + + IN23_WIDTH + In23 Width + 1 + + + IN24_WIDTH + In24 Width + 1 + + + IN25_WIDTH + In25 Width + 1 + + + IN26_WIDTH + In26 Width + 1 + + + IN27_WIDTH + In27 Width + 1 + + + IN28_WIDTH + In28 Width + 1 + + + IN29_WIDTH + In29 Width + 1 + + + IN30_WIDTH + In30 Width + 1 + + + IN31_WIDTH + In31 Width + 1 + + + IN32_WIDTH + In32 Width + 1 + + + IN33_WIDTH + In33 Width + 1 + + + IN34_WIDTH + In34 Width + 1 + + + IN35_WIDTH + In35 Width + 1 + + + IN36_WIDTH + In36 Width + 1 + + + IN37_WIDTH + In37 Width + 1 + + + IN38_WIDTH + In38 Width + 1 + + + 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+ + + IN98_WIDTH + In98 Width + 1 + + + IN99_WIDTH + In99 Width + 1 + + + IN100_WIDTH + In100 Width + 1 + + + IN101_WIDTH + In101 Width + 1 + + + IN102_WIDTH + In102 Width + 1 + + + IN103_WIDTH + In103 Width + 1 + + + IN104_WIDTH + In104 Width + 1 + + + IN105_WIDTH + In105 Width + 1 + + + IN106_WIDTH + In106 Width + 1 + + + IN107_WIDTH + In107 Width + 1 + + + IN108_WIDTH + In108 Width + 1 + + + IN109_WIDTH + In109 Width + 1 + + + IN110_WIDTH + In110 Width + 1 + + + IN111_WIDTH + In111 Width + 1 + + + IN112_WIDTH + In112 Width + 1 + + + IN113_WIDTH + In113 Width + 1 + + + IN114_WIDTH + In114 Width + 1 + + + IN115_WIDTH + In115 Width + 1 + + + IN116_WIDTH + In116 Width + 1 + + + IN117_WIDTH + In117 Width + 1 + + + IN118_WIDTH + In118 Width + 1 + + + IN119_WIDTH + In119 Width + 1 + + + IN120_WIDTH + In120 Width + 1 + + + IN121_WIDTH + In121 Width + 1 + + + IN122_WIDTH + In122 Width + 1 + + + IN123_WIDTH + In123 Width + 1 + + + IN124_WIDTH + In124 Width + 1 + + + IN125_WIDTH + In125 Width + 1 + + + IN126_WIDTH + In126 Width + 1 + + + IN127_WIDTH + In127 Width + 1 + + + dout_width + Dout Width + 2 + + + + + Concat + 4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v new file mode 100644 index 0000000..25b5d97 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v @@ -0,0 +1,328 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 4 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlconcat_0_0 ( + In0, + In1, + dout +); + +input wire [0 : 0] In0; +input wire [0 : 0] In1; +output wire [1 : 0] dout; + + xlconcat_v2_1_4_xlconcat #( + .IN0_WIDTH(1), + .IN1_WIDTH(1), + .IN2_WIDTH(1), + .IN3_WIDTH(1), + .IN4_WIDTH(1), + .IN5_WIDTH(1), + .IN6_WIDTH(1), + .IN7_WIDTH(1), + .IN8_WIDTH(1), + .IN9_WIDTH(1), + .IN10_WIDTH(1), + .IN11_WIDTH(1), + .IN12_WIDTH(1), + .IN13_WIDTH(1), + .IN14_WIDTH(1), + .IN15_WIDTH(1), + .IN16_WIDTH(1), + .IN17_WIDTH(1), + .IN18_WIDTH(1), + .IN19_WIDTH(1), + .IN20_WIDTH(1), + .IN21_WIDTH(1), + .IN22_WIDTH(1), + .IN23_WIDTH(1), + .IN24_WIDTH(1), + .IN25_WIDTH(1), + .IN26_WIDTH(1), + .IN27_WIDTH(1), + .IN28_WIDTH(1), + .IN29_WIDTH(1), + .IN30_WIDTH(1), + .IN31_WIDTH(1), + .IN32_WIDTH(1), + .IN33_WIDTH(1), + .IN34_WIDTH(1), + .IN35_WIDTH(1), + .IN36_WIDTH(1), + .IN37_WIDTH(1), + .IN38_WIDTH(1), + .IN39_WIDTH(1), + .IN40_WIDTH(1), + .IN41_WIDTH(1), + .IN42_WIDTH(1), + .IN43_WIDTH(1), + .IN44_WIDTH(1), + .IN45_WIDTH(1), + .IN46_WIDTH(1), + .IN47_WIDTH(1), + .IN48_WIDTH(1), + .IN49_WIDTH(1), + .IN50_WIDTH(1), + .IN51_WIDTH(1), + .IN52_WIDTH(1), + .IN53_WIDTH(1), + .IN54_WIDTH(1), + .IN55_WIDTH(1), + .IN56_WIDTH(1), + .IN57_WIDTH(1), + .IN58_WIDTH(1), + .IN59_WIDTH(1), + .IN60_WIDTH(1), + .IN61_WIDTH(1), + .IN62_WIDTH(1), + .IN63_WIDTH(1), + .IN64_WIDTH(1), + .IN65_WIDTH(1), + .IN66_WIDTH(1), + .IN67_WIDTH(1), + .IN68_WIDTH(1), + .IN69_WIDTH(1), + .IN70_WIDTH(1), + .IN71_WIDTH(1), + .IN72_WIDTH(1), + .IN73_WIDTH(1), + .IN74_WIDTH(1), + .IN75_WIDTH(1), + .IN76_WIDTH(1), + .IN77_WIDTH(1), + .IN78_WIDTH(1), + .IN79_WIDTH(1), + .IN80_WIDTH(1), + .IN81_WIDTH(1), + .IN82_WIDTH(1), + .IN83_WIDTH(1), + .IN84_WIDTH(1), + .IN85_WIDTH(1), + .IN86_WIDTH(1), + .IN87_WIDTH(1), + .IN88_WIDTH(1), + .IN89_WIDTH(1), + .IN90_WIDTH(1), + .IN91_WIDTH(1), + .IN92_WIDTH(1), + .IN93_WIDTH(1), + .IN94_WIDTH(1), + .IN95_WIDTH(1), + .IN96_WIDTH(1), + .IN97_WIDTH(1), + .IN98_WIDTH(1), + .IN99_WIDTH(1), + .IN100_WIDTH(1), + .IN101_WIDTH(1), + .IN102_WIDTH(1), + .IN103_WIDTH(1), + .IN104_WIDTH(1), + .IN105_WIDTH(1), + .IN106_WIDTH(1), + .IN107_WIDTH(1), + .IN108_WIDTH(1), + .IN109_WIDTH(1), + .IN110_WIDTH(1), + .IN111_WIDTH(1), + .IN112_WIDTH(1), + .IN113_WIDTH(1), + .IN114_WIDTH(1), + .IN115_WIDTH(1), + .IN116_WIDTH(1), + .IN117_WIDTH(1), + .IN118_WIDTH(1), + .IN119_WIDTH(1), + .IN120_WIDTH(1), + .IN121_WIDTH(1), + .IN122_WIDTH(1), + .IN123_WIDTH(1), + .IN124_WIDTH(1), + .IN125_WIDTH(1), + .IN126_WIDTH(1), + .IN127_WIDTH(1), + .dout_width(2), + .NUM_PORTS(2) + ) inst ( + .In0(In0), + .In1(In1), + .In2(1'B0), + .In3(1'B0), + .In4(1'B0), + .In5(1'B0), + .In6(1'B0), + .In7(1'B0), + .In8(1'B0), + .In9(1'B0), + .In10(1'B0), + .In11(1'B0), + .In12(1'B0), + .In13(1'B0), + .In14(1'B0), + .In15(1'B0), + .In16(1'B0), + .In17(1'B0), + .In18(1'B0), + .In19(1'B0), + .In20(1'B0), + .In21(1'B0), + .In22(1'B0), + .In23(1'B0), + .In24(1'B0), + .In25(1'B0), + .In26(1'B0), + .In27(1'B0), + .In28(1'B0), + .In29(1'B0), + .In30(1'B0), + .In31(1'B0), + .In32(1'B0), + .In33(1'B0), + .In34(1'B0), + .In35(1'B0), + .In36(1'B0), + .In37(1'B0), + .In38(1'B0), + .In39(1'B0), + .In40(1'B0), + .In41(1'B0), + .In42(1'B0), + .In43(1'B0), + .In44(1'B0), + .In45(1'B0), + .In46(1'B0), + .In47(1'B0), + .In48(1'B0), + .In49(1'B0), + .In50(1'B0), + .In51(1'B0), + .In52(1'B0), + .In53(1'B0), + .In54(1'B0), + .In55(1'B0), + .In56(1'B0), + .In57(1'B0), + .In58(1'B0), + .In59(1'B0), + .In60(1'B0), + .In61(1'B0), + .In62(1'B0), + .In63(1'B0), + .In64(1'B0), + .In65(1'B0), + .In66(1'B0), + .In67(1'B0), + .In68(1'B0), + .In69(1'B0), + .In70(1'B0), + .In71(1'B0), + .In72(1'B0), + .In73(1'B0), + .In74(1'B0), + .In75(1'B0), + .In76(1'B0), + .In77(1'B0), + .In78(1'B0), + .In79(1'B0), + .In80(1'B0), + .In81(1'B0), + .In82(1'B0), + .In83(1'B0), + .In84(1'B0), + .In85(1'B0), + .In86(1'B0), + .In87(1'B0), + .In88(1'B0), + .In89(1'B0), + .In90(1'B0), + .In91(1'B0), + .In92(1'B0), + .In93(1'B0), + .In94(1'B0), + .In95(1'B0), + .In96(1'B0), + .In97(1'B0), + .In98(1'B0), + .In99(1'B0), + .In100(1'B0), + .In101(1'B0), + .In102(1'B0), + .In103(1'B0), + .In104(1'B0), + .In105(1'B0), + .In106(1'B0), + .In107(1'B0), + .In108(1'B0), + .In109(1'B0), + .In110(1'B0), + .In111(1'B0), + .In112(1'B0), + .In113(1'B0), + .In114(1'B0), + .In115(1'B0), + .In116(1'B0), + .In117(1'B0), + .In118(1'B0), + .In119(1'B0), + .In120(1'B0), + .In121(1'B0), + .In122(1'B0), + .In123(1'B0), + .In124(1'B0), + .In125(1'B0), + .In126(1'B0), + .In127(1'B0), + .dout(dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/synth/design_1_xlconcat_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/synth/design_1_xlconcat_0_0.v new file mode 100644 index 0000000..96ea47b --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/synth/design_1_xlconcat_0_0.v @@ -0,0 +1,332 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconcat:2.1 +// IP Revision: 4 + +(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2020.2" *) +(* CHECK_LICENSE_TYPE = "design_1_xlconcat_0_0,xlconcat_v2_1_4_xlconcat,{}" *) +(* CORE_GENERATION_INFO = "design_1_xlconcat_0_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WI\ +DTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,\ +IN62_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_\ +WIDTH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlconcat_0_0 ( + In0, + In1, + dout +); + +input wire [0 : 0] In0; +input wire [0 : 0] In1; +output wire [1 : 0] dout; + + xlconcat_v2_1_4_xlconcat #( + .IN0_WIDTH(1), + .IN1_WIDTH(1), + .IN2_WIDTH(1), + .IN3_WIDTH(1), + .IN4_WIDTH(1), + .IN5_WIDTH(1), + .IN6_WIDTH(1), + .IN7_WIDTH(1), + .IN8_WIDTH(1), + .IN9_WIDTH(1), + .IN10_WIDTH(1), + .IN11_WIDTH(1), + .IN12_WIDTH(1), + .IN13_WIDTH(1), + .IN14_WIDTH(1), + .IN15_WIDTH(1), + .IN16_WIDTH(1), + .IN17_WIDTH(1), + .IN18_WIDTH(1), + .IN19_WIDTH(1), + .IN20_WIDTH(1), + .IN21_WIDTH(1), + .IN22_WIDTH(1), + .IN23_WIDTH(1), + .IN24_WIDTH(1), + .IN25_WIDTH(1), + .IN26_WIDTH(1), + .IN27_WIDTH(1), + .IN28_WIDTH(1), + .IN29_WIDTH(1), + .IN30_WIDTH(1), + .IN31_WIDTH(1), + .IN32_WIDTH(1), + .IN33_WIDTH(1), + .IN34_WIDTH(1), + .IN35_WIDTH(1), + .IN36_WIDTH(1), + .IN37_WIDTH(1), + .IN38_WIDTH(1), + .IN39_WIDTH(1), + .IN40_WIDTH(1), + .IN41_WIDTH(1), + .IN42_WIDTH(1), + .IN43_WIDTH(1), + .IN44_WIDTH(1), + .IN45_WIDTH(1), + .IN46_WIDTH(1), + .IN47_WIDTH(1), + .IN48_WIDTH(1), + .IN49_WIDTH(1), + .IN50_WIDTH(1), + .IN51_WIDTH(1), + .IN52_WIDTH(1), + .IN53_WIDTH(1), + .IN54_WIDTH(1), + .IN55_WIDTH(1), + .IN56_WIDTH(1), + .IN57_WIDTH(1), + .IN58_WIDTH(1), + .IN59_WIDTH(1), + .IN60_WIDTH(1), + .IN61_WIDTH(1), + .IN62_WIDTH(1), + .IN63_WIDTH(1), + .IN64_WIDTH(1), + .IN65_WIDTH(1), + .IN66_WIDTH(1), + .IN67_WIDTH(1), + .IN68_WIDTH(1), + .IN69_WIDTH(1), + .IN70_WIDTH(1), + .IN71_WIDTH(1), + .IN72_WIDTH(1), + .IN73_WIDTH(1), + .IN74_WIDTH(1), + .IN75_WIDTH(1), + .IN76_WIDTH(1), + .IN77_WIDTH(1), + .IN78_WIDTH(1), + .IN79_WIDTH(1), + .IN80_WIDTH(1), + .IN81_WIDTH(1), + .IN82_WIDTH(1), + .IN83_WIDTH(1), + .IN84_WIDTH(1), + .IN85_WIDTH(1), + .IN86_WIDTH(1), + .IN87_WIDTH(1), + .IN88_WIDTH(1), + .IN89_WIDTH(1), + .IN90_WIDTH(1), + .IN91_WIDTH(1), + .IN92_WIDTH(1), + .IN93_WIDTH(1), + .IN94_WIDTH(1), + .IN95_WIDTH(1), + .IN96_WIDTH(1), + .IN97_WIDTH(1), + .IN98_WIDTH(1), + .IN99_WIDTH(1), + .IN100_WIDTH(1), + .IN101_WIDTH(1), + .IN102_WIDTH(1), + .IN103_WIDTH(1), + .IN104_WIDTH(1), + .IN105_WIDTH(1), + .IN106_WIDTH(1), + .IN107_WIDTH(1), + .IN108_WIDTH(1), + .IN109_WIDTH(1), + .IN110_WIDTH(1), + .IN111_WIDTH(1), + .IN112_WIDTH(1), + .IN113_WIDTH(1), + .IN114_WIDTH(1), + .IN115_WIDTH(1), + .IN116_WIDTH(1), + .IN117_WIDTH(1), + .IN118_WIDTH(1), + .IN119_WIDTH(1), + .IN120_WIDTH(1), + .IN121_WIDTH(1), + .IN122_WIDTH(1), + .IN123_WIDTH(1), + .IN124_WIDTH(1), + .IN125_WIDTH(1), + .IN126_WIDTH(1), + .IN127_WIDTH(1), + .dout_width(2), + .NUM_PORTS(2) + ) inst ( + .In0(In0), + .In1(In1), + .In2(1'B0), + .In3(1'B0), + .In4(1'B0), + .In5(1'B0), + .In6(1'B0), + .In7(1'B0), + .In8(1'B0), + .In9(1'B0), + .In10(1'B0), + .In11(1'B0), + .In12(1'B0), + .In13(1'B0), + .In14(1'B0), + .In15(1'B0), + .In16(1'B0), + .In17(1'B0), + .In18(1'B0), + .In19(1'B0), + .In20(1'B0), + .In21(1'B0), + .In22(1'B0), + .In23(1'B0), + .In24(1'B0), + .In25(1'B0), + .In26(1'B0), + .In27(1'B0), + .In28(1'B0), + .In29(1'B0), + .In30(1'B0), + .In31(1'B0), + .In32(1'B0), + .In33(1'B0), + .In34(1'B0), + .In35(1'B0), + .In36(1'B0), + .In37(1'B0), + .In38(1'B0), + .In39(1'B0), + .In40(1'B0), + .In41(1'B0), + .In42(1'B0), + .In43(1'B0), + .In44(1'B0), + .In45(1'B0), + .In46(1'B0), + .In47(1'B0), + .In48(1'B0), + .In49(1'B0), + .In50(1'B0), + .In51(1'B0), + .In52(1'B0), + .In53(1'B0), + .In54(1'B0), + .In55(1'B0), + .In56(1'B0), + .In57(1'B0), + .In58(1'B0), + .In59(1'B0), + .In60(1'B0), + .In61(1'B0), + .In62(1'B0), + .In63(1'B0), + .In64(1'B0), + .In65(1'B0), + .In66(1'B0), + .In67(1'B0), + .In68(1'B0), + .In69(1'B0), + .In70(1'B0), + .In71(1'B0), + .In72(1'B0), + .In73(1'B0), + .In74(1'B0), + .In75(1'B0), + .In76(1'B0), + .In77(1'B0), + .In78(1'B0), + .In79(1'B0), + .In80(1'B0), + .In81(1'B0), + .In82(1'B0), + .In83(1'B0), + .In84(1'B0), + .In85(1'B0), + .In86(1'B0), + .In87(1'B0), + .In88(1'B0), + .In89(1'B0), + .In90(1'B0), + .In91(1'B0), + .In92(1'B0), + .In93(1'B0), + .In94(1'B0), + .In95(1'B0), + .In96(1'B0), + .In97(1'B0), + .In98(1'B0), + .In99(1'B0), + .In100(1'B0), + .In101(1'B0), + .In102(1'B0), + .In103(1'B0), + .In104(1'B0), + .In105(1'B0), + .In106(1'B0), + .In107(1'B0), + .In108(1'B0), + .In109(1'B0), + .In110(1'B0), + .In111(1'B0), + .In112(1'B0), + .In113(1'B0), + .In114(1'B0), + .In115(1'B0), + .In116(1'B0), + .In117(1'B0), + .In118(1'B0), + .In119(1'B0), + .In120(1'B0), + .In121(1'B0), + .In122(1'B0), + .In123(1'B0), + .In124(1'B0), + .In125(1'B0), + .In126(1'B0), + .In127(1'B0), + .dout(dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0_1/design_1_xlconcat_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0_1/design_1_xlconcat_0_0.xml new file mode 100644 index 0000000..6a0e5e8 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0_1/design_1_xlconcat_0_0.xml @@ -0,0 +1,4808 @@ + + + xilinx.com + customized_ip + design_1_xlconcat_0_0 + 1.0 + + + + In0 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + true + + + + + + In1 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + true + + + + + + In2 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + In3 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + In4 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + In5 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + In6 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + In7 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + In8 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + In9 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + In10 + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + 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systemCSource:vivado.xilinx.com:simulation + systemc + xlconstant_v1_1_7 + + xilinx_systemcsimulation_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:b1d24631 + + + sim_type + tlm + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + design_1_xlconstant_0_0 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:b1d24631 + + + + + xilinx_systemcsimulationwrapper + SystemC Simulation Wrapper + systemCSource:vivado.xilinx.com:simulation.wrapper + systemc + design_1_xlconstant_0_0 + + xilinx_systemcsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:b1d24631 + + + sim_type + tlm + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + xlconstant_v1_1_7_xlconstant + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:1027ac22 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:1027ac22 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + design_1_xlconstant_0_0 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:1027ac22 + + + + + + + dout + + out + + 7 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + CONST_WIDTH + Const Width + 8 + + + CONST_VAL + Const Val + 0x00 + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + xlconstant_v1_1_7 + + + + xilinx_systemcsimulation_view_fileset + + sim/xlconstant_v1_1_7.h + systemCSource + true + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/design_1_xlconstant_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/design_1_xlconstant_0_0.h + systemCSource + true + + + sim/design_1_xlconstant_0_0.cpp + systemCSource + + + sim/design_1_xlconstant_0_0_stub.sv + systemVerilogSource + + + + xilinx_verilogsynthesis_view_fileset + + ../../ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + xlconstant_v1_1_7 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/design_1_xlconstant_0_0.v + verilogSource + xil_defaultlib + + + + Gives a constant signed value. + + + Component_Name + design_1_xlconstant_0_0 + + + CONST_WIDTH + Const Width + 8 + + + CONST_VAL + Const Val + 0 + + + + + Constant + 7 + + + + + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.h new file mode 100644 index 0000000..f1321c6 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.h @@ -0,0 +1,65 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _design_1_xlconstant_0_0_H_ +#define _design_1_xlconstant_0_0_H_ + +#include "xlconstant_v1_1_7.h" +#include "systemc.h" +class design_1_xlconstant_0_0 : public sc_module { + public: +xlconstant_v1_1_7<8,0> mod; + sc_out< sc_bv<8> > dout; +design_1_xlconstant_0_0 (sc_core::sc_module_name name); + }; + +#endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v new file mode 100644 index 0000000..a112873 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v @@ -0,0 +1,68 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 7 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlconstant_0_0 ( + dout +); + +output wire [7 : 0] dout; + + xlconstant_v1_1_7_xlconstant #( + .CONST_WIDTH(8), + .CONST_VAL(8'H00) + ) inst ( + .dout(dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0_stub.sv b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0_stub.sv new file mode 100644 index 0000000..69b0562 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0_stub.sv @@ -0,0 +1,86 @@ +// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +//------------------------------------------------------------------------------------ +// Filename: xl_Constant_stub.sv +// Description: This HDL file is intended to be used with following simulators only: +// +// Vivado Simulator (XSim) +// Cadence Xcelium Simulator +// Aldec Riviera-PRO Simulator +// +//------------------------------------------------------------------------------------ +`ifdef XILINX_SIMULATOR +`ifndef XILINX_SIMULATOR_BITASBOOL +`define XILINX_SIMULATOR_BITASBOOL +typedef bit bit_as_bool; +`endif + +(* SC_MODULE_EXPORT *) +module design_1_xlconstant_0_0 ( + output bit [7 : 0 ] dout +); +endmodule +`endif + +`ifdef XCELIUM +(* XMSC_MODULE_EXPORT *) +module design_1_xlconstant_0_0 (dout) +(* integer foreign = "SystemC"; +*); + output wire [7 : 0 ] dout; +endmodule +`endif + +`ifdef RIVIERA +(* SC_MODULE_EXPORT *) +module design_1_xlconstant_0_0 (dout) + output wire [7 : 0 ] dout; +endmodule +`endif + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h new file mode 100644 index 0000000..434d287 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _xlconstant_v1_1_7_H_ +#define _xlconstant_v1_1_7_H_ + +#include "systemc.h" +template +SC_MODULE(xlconstant_v1_1_7) { + public: + sc_out< sc_bv > dout; + void init() { + dout.write(CONST_VAL); + } + SC_CTOR(xlconstant_v1_1_7) { + SC_METHOD(init); + } +}; + +#endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/synth/design_1_xlconstant_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/synth/design_1_xlconstant_0_0.v new file mode 100644 index 0000000..239a973 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/synth/design_1_xlconstant_0_0.v @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 7 + +(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2020.2" *) +(* CHECK_LICENSE_TYPE = "design_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{}" *) +(* CORE_GENERATION_INFO = "design_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=8,CONST_VAL=0x00}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlconstant_0_0 ( + dout +); + +output wire [7 : 0] dout; + + xlconstant_v1_1_7_xlconstant #( + .CONST_WIDTH(8), + .CONST_VAL(8'H00) + ) inst ( + .dout(dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0_1/design_1_xlconstant_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0_1/design_1_xlconstant_0_0.xml new file mode 100644 index 0000000..82838a6 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0_1/design_1_xlconstant_0_0.xml @@ -0,0 +1,69 @@ + + + xilinx.com + customized_ip + design_1_xlconstant_0_0 + 1.0 + + + + dout + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + CONST_WIDTH + Const Width + 1 + + + CONST_VAL + Const Val + 0x1 + + + + Gives a constant signed value. + + + Component_Name + design_1_xlconstant_0_0 + + + CONST_WIDTH + Const Width + 1 + + + CONST_VAL + Const Val + 1 + + + + + Constant + 7 + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/design_1_xlconstant_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/design_1_xlconstant_0_1.xml new file mode 100644 index 0000000..cc7dfd5 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/design_1_xlconstant_0_1.xml @@ -0,0 +1,270 @@ + + + xilinx.com + customized_ip + design_1_xlconstant_0_1 + 1.0 + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + xlconstant_v1_1_7_xlconstant + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:f85b49be + + + + + xilinx_systemcsimulation + SystemC Simulation + systemCSource:vivado.xilinx.com:simulation + systemc + xlconstant_v1_1_7 + + xilinx_systemcsimulation_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:f85b49be + + + sim_type + tlm + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + design_1_xlconstant_0_1 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:f85b49be + + + + + xilinx_systemcsimulationwrapper + SystemC Simulation Wrapper + systemCSource:vivado.xilinx.com:simulation.wrapper + systemc + design_1_xlconstant_0_1 + + xilinx_systemcsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:f85b49be + + + sim_type + tlm + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + xlconstant_v1_1_7_xlconstant + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:2a848199 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:2a848199 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + design_1_xlconstant_0_1 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:2a848199 + + + + + + + dout + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + CONST_WIDTH + Const Width + 1 + + + CONST_VAL + Const Val + 0x1 + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + xlconstant_v1_1_7 + + + + xilinx_systemcsimulation_view_fileset + + sim/xlconstant_v1_1_7.h + systemCSource + true + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/design_1_xlconstant_0_1.v + verilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/design_1_xlconstant_0_1.h + systemCSource + true + + + sim/design_1_xlconstant_0_1.cpp + systemCSource + + + sim/design_1_xlconstant_0_1_stub.sv + systemVerilogSource + + + + xilinx_verilogsynthesis_view_fileset + + ../../ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + xlconstant_v1_1_7 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/design_1_xlconstant_0_1.v + verilogSource + xil_defaultlib + + + + Gives a constant signed value. + + + Component_Name + design_1_xlconstant_0_1 + + + CONST_WIDTH + Const Width + 1 + + + CONST_VAL + Const Val + 1 + + + + + Constant + 7 + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.h new file mode 100644 index 0000000..c1a0432 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.h @@ -0,0 +1,65 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _design_1_xlconstant_0_1_H_ +#define _design_1_xlconstant_0_1_H_ + +#include "xlconstant_v1_1_7.h" +#include "systemc.h" +class design_1_xlconstant_0_1 : public sc_module { + public: +xlconstant_v1_1_7<1,1> mod; + sc_out< sc_bv<1> > dout; +design_1_xlconstant_0_1 (sc_core::sc_module_name name); + }; + +#endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v new file mode 100644 index 0000000..31c4f41 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v @@ -0,0 +1,68 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 7 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlconstant_0_1 ( + dout +); + +output wire [0 : 0] dout; + + xlconstant_v1_1_7_xlconstant #( + .CONST_WIDTH(1), + .CONST_VAL(1'H1) + ) inst ( + .dout(dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1_stub.sv b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1_stub.sv new file mode 100644 index 0000000..1ececcc --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1_stub.sv @@ -0,0 +1,86 @@ +// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +//------------------------------------------------------------------------------------ +// Filename: xl_Constant_stub.sv +// Description: This HDL file is intended to be used with following simulators only: +// +// Vivado Simulator (XSim) +// Cadence Xcelium Simulator +// Aldec Riviera-PRO Simulator +// +//------------------------------------------------------------------------------------ +`ifdef XILINX_SIMULATOR +`ifndef XILINX_SIMULATOR_BITASBOOL +`define XILINX_SIMULATOR_BITASBOOL +typedef bit bit_as_bool; +`endif + +(* SC_MODULE_EXPORT *) +module design_1_xlconstant_0_1 ( + output bit [0 : 0 ] dout +); +endmodule +`endif + +`ifdef XCELIUM +(* XMSC_MODULE_EXPORT *) +module design_1_xlconstant_0_1 (dout) +(* integer foreign = "SystemC"; +*); + output wire [0 : 0 ] dout; +endmodule +`endif + +`ifdef RIVIERA +(* SC_MODULE_EXPORT *) +module design_1_xlconstant_0_1 (dout) + output wire [0 : 0 ] dout; +endmodule +`endif + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/xlconstant_v1_1_7.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/xlconstant_v1_1_7.h new file mode 100644 index 0000000..434d287 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/xlconstant_v1_1_7.h @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _xlconstant_v1_1_7_H_ +#define _xlconstant_v1_1_7_H_ + +#include "systemc.h" +template +SC_MODULE(xlconstant_v1_1_7) { + public: + sc_out< sc_bv > dout; + void init() { + dout.write(CONST_VAL); + } + SC_CTOR(xlconstant_v1_1_7) { + SC_METHOD(init); + } +}; + +#endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/synth/design_1_xlconstant_0_1.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/synth/design_1_xlconstant_0_1.v new file mode 100644 index 0000000..5b9fbaa --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/synth/design_1_xlconstant_0_1.v @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 7 + +(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2020.2" *) +(* CHECK_LICENSE_TYPE = "design_1_xlconstant_0_1,xlconstant_v1_1_7_xlconstant,{}" *) +(* CORE_GENERATION_INFO = "design_1_xlconstant_0_1,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlconstant_0_1 ( + dout +); + +output wire [0 : 0] dout; + + xlconstant_v1_1_7_xlconstant #( + .CONST_WIDTH(1), + .CONST_VAL(1'H1) + ) inst ( + .dout(dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1_1/design_1_xlconstant_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1_1/design_1_xlconstant_0_1.xml new file mode 100644 index 0000000..cf4bf5b --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1_1/design_1_xlconstant_0_1.xml @@ -0,0 +1,69 @@ + + + xilinx.com + customized_ip + design_1_xlconstant_0_1 + 1.0 + + + + dout + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + CONST_WIDTH + Const Width + 1 + + + CONST_VAL + Const Val + 0x1 + + + + Gives a constant signed value. + + + Component_Name + design_1_xlconstant_0_1 + + + CONST_WIDTH + Const Width + 1 + + + CONST_VAL + Const Val + 1 + + + + + Constant + 7 + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/design_1_xlconstant_0_2.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/design_1_xlconstant_0_2.xml new file mode 100644 index 0000000..74b403f --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/design_1_xlconstant_0_2.xml @@ -0,0 +1,270 @@ + + + xilinx.com + customized_ip + design_1_xlconstant_0_2 + 1.0 + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + xlconstant_v1_1_7_xlconstant + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:e4c63470 + + + + + xilinx_systemcsimulation + SystemC Simulation + systemCSource:vivado.xilinx.com:simulation + systemc + xlconstant_v1_1_7 + + xilinx_systemcsimulation_view_fileset + + + + GENtimestamp + Tue Jan 16 16:48:36 UTC 2024 + + + outputProductCRC + 9:e4c63470 + + + sim_type + tlm + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + design_1_xlconstant_0_2 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:48:36 UTC 2024 + + + outputProductCRC + 9:e4c63470 + + + + + xilinx_systemcsimulationwrapper + SystemC Simulation Wrapper + systemCSource:vivado.xilinx.com:simulation.wrapper + systemc + design_1_xlconstant_0_2 + + xilinx_systemcsimulationwrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:48:37 UTC 2024 + + + outputProductCRC + 9:e4c63470 + + + sim_type + tlm + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + xlconstant_v1_1_7_xlconstant + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:58845e65 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:58845e65 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + design_1_xlconstant_0_2 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:58845e65 + + + + + + + dout + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + CONST_WIDTH + Const Width + 1 + + + CONST_VAL + Const Val + 0x1 + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + xlconstant_v1_1_7 + + + + xilinx_systemcsimulation_view_fileset + + sim/xlconstant_v1_1_7.h + systemCSource + true + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/design_1_xlconstant_0_2.v + verilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/design_1_xlconstant_0_2.h + systemCSource + true + + + sim/design_1_xlconstant_0_2.cpp + systemCSource + + + sim/design_1_xlconstant_0_2_stub.sv + systemVerilogSource + + + + xilinx_verilogsynthesis_view_fileset + + ../../ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + xlconstant_v1_1_7 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/design_1_xlconstant_0_2.v + verilogSource + xil_defaultlib + + + + Gives a constant signed value. + + + Component_Name + design_1_xlconstant_0_2 + + + CONST_WIDTH + Const Width + 1 + + + CONST_VAL + Const Val + 1 + + + + + Constant + 7 + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.h new file mode 100644 index 0000000..f81da77 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.h @@ -0,0 +1,65 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _design_1_xlconstant_0_2_H_ +#define _design_1_xlconstant_0_2_H_ + +#include "xlconstant_v1_1_7.h" +#include "systemc.h" +class design_1_xlconstant_0_2 : public sc_module { + public: +xlconstant_v1_1_7<1,1> mod; + sc_out< sc_bv<1> > dout; +design_1_xlconstant_0_2 (sc_core::sc_module_name name); + }; + +#endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v new file mode 100644 index 0000000..5011eda --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v @@ -0,0 +1,68 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 7 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlconstant_0_2 ( + dout +); + +output wire [0 : 0] dout; + + xlconstant_v1_1_7_xlconstant #( + .CONST_WIDTH(1), + .CONST_VAL(1'H1) + ) inst ( + .dout(dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2_stub.sv b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2_stub.sv new file mode 100644 index 0000000..769cc9b --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2_stub.sv @@ -0,0 +1,86 @@ +// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +//------------------------------------------------------------------------------------ +// Filename: xl_Constant_stub.sv +// Description: This HDL file is intended to be used with following simulators only: +// +// Vivado Simulator (XSim) +// Cadence Xcelium Simulator +// Aldec Riviera-PRO Simulator +// +//------------------------------------------------------------------------------------ +`ifdef XILINX_SIMULATOR +`ifndef XILINX_SIMULATOR_BITASBOOL +`define XILINX_SIMULATOR_BITASBOOL +typedef bit bit_as_bool; +`endif + +(* SC_MODULE_EXPORT *) +module design_1_xlconstant_0_2 ( + output bit [0 : 0 ] dout +); +endmodule +`endif + +`ifdef XCELIUM +(* XMSC_MODULE_EXPORT *) +module design_1_xlconstant_0_2 (dout) +(* integer foreign = "SystemC"; +*); + output wire [0 : 0 ] dout; +endmodule +`endif + +`ifdef RIVIERA +(* SC_MODULE_EXPORT *) +module design_1_xlconstant_0_2 (dout) + output wire [0 : 0 ] dout; +endmodule +`endif + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/xlconstant_v1_1_7.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/xlconstant_v1_1_7.h new file mode 100644 index 0000000..434d287 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/xlconstant_v1_1_7.h @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _xlconstant_v1_1_7_H_ +#define _xlconstant_v1_1_7_H_ + +#include "systemc.h" +template +SC_MODULE(xlconstant_v1_1_7) { + public: + sc_out< sc_bv > dout; + void init() { + dout.write(CONST_VAL); + } + SC_CTOR(xlconstant_v1_1_7) { + SC_METHOD(init); + } +}; + +#endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/synth/design_1_xlconstant_0_2.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/synth/design_1_xlconstant_0_2.v new file mode 100644 index 0000000..92f6a90 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/synth/design_1_xlconstant_0_2.v @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 7 + +(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2020.2" *) +(* CHECK_LICENSE_TYPE = "design_1_xlconstant_0_2,xlconstant_v1_1_7_xlconstant,{}" *) +(* CORE_GENERATION_INFO = "design_1_xlconstant_0_2,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlconstant_0_2 ( + dout +); + +output wire [0 : 0] dout; + + xlconstant_v1_1_7_xlconstant #( + .CONST_WIDTH(1), + .CONST_VAL(1'H1) + ) inst ( + .dout(dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/design_1_xlconstant_0_3.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/design_1_xlconstant_0_3.xml new file mode 100644 index 0000000..4e061df --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/design_1_xlconstant_0_3.xml @@ -0,0 +1,273 @@ + + + xilinx.com + customized_ip + design_1_xlconstant_0_3 + 1.0 + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + xlconstant_v1_1_7_xlconstant + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:1c71643f + + + + + xilinx_systemcsimulation + SystemC Simulation + systemCSource:vivado.xilinx.com:simulation + systemc + xlconstant_v1_1_7 + + xilinx_systemcsimulation_view_fileset + + + + GENtimestamp + Tue Jan 16 16:48:37 UTC 2024 + + + outputProductCRC + 9:1c71643f + + + sim_type + tlm + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + design_1_xlconstant_0_3 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:48:37 UTC 2024 + + + outputProductCRC + 9:1c71643f + + + + + xilinx_systemcsimulationwrapper + SystemC Simulation Wrapper + systemCSource:vivado.xilinx.com:simulation.wrapper + systemc + design_1_xlconstant_0_3 + + xilinx_systemcsimulationwrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:48:37 UTC 2024 + + + outputProductCRC + 9:1c71643f + + + sim_type + tlm + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + xlconstant_v1_1_7_xlconstant + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:9a42c9c2 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:9a42c9c2 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + design_1_xlconstant_0_3 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:07 UTC 2024 + + + outputProductCRC + 9:9a42c9c2 + + + + + + + dout + + out + + 23 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + CONST_WIDTH + Const Width + 24 + + + CONST_VAL + Const Val + 0x000001 + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + xlconstant_v1_1_7 + + + + xilinx_systemcsimulation_view_fileset + + sim/xlconstant_v1_1_7.h + systemCSource + true + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/design_1_xlconstant_0_3.v + verilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/design_1_xlconstant_0_3.h + systemCSource + true + + + sim/design_1_xlconstant_0_3.cpp + systemCSource + + + sim/design_1_xlconstant_0_3_stub.sv + systemVerilogSource + + + + xilinx_verilogsynthesis_view_fileset + + ../../ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v + verilogSource + xlconstant_v1_1_7 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/design_1_xlconstant_0_3.v + verilogSource + xil_defaultlib + + + + Gives a constant signed value. + + + Component_Name + design_1_xlconstant_0_3 + + + CONST_WIDTH + Const Width + 24 + + + CONST_VAL + Const Val + 1 + + + + + Constant + 7 + + + + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.h new file mode 100644 index 0000000..58f2af3 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.h @@ -0,0 +1,65 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _design_1_xlconstant_0_3_H_ +#define _design_1_xlconstant_0_3_H_ + +#include "xlconstant_v1_1_7.h" +#include "systemc.h" +class design_1_xlconstant_0_3 : public sc_module { + public: +xlconstant_v1_1_7<24,1> mod; + sc_out< sc_bv<24> > dout; +design_1_xlconstant_0_3 (sc_core::sc_module_name name); + }; + +#endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v new file mode 100644 index 0000000..65ddfe3 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v @@ -0,0 +1,68 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 7 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlconstant_0_3 ( + dout +); + +output wire [23 : 0] dout; + + xlconstant_v1_1_7_xlconstant #( + .CONST_WIDTH(24), + .CONST_VAL(24'H000001) + ) inst ( + .dout(dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3_stub.sv b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3_stub.sv new file mode 100644 index 0000000..931a227 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3_stub.sv @@ -0,0 +1,86 @@ +// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +//------------------------------------------------------------------------------------ +// Filename: xl_Constant_stub.sv +// Description: This HDL file is intended to be used with following simulators only: +// +// Vivado Simulator (XSim) +// Cadence Xcelium Simulator +// Aldec Riviera-PRO Simulator +// +//------------------------------------------------------------------------------------ +`ifdef XILINX_SIMULATOR +`ifndef XILINX_SIMULATOR_BITASBOOL +`define XILINX_SIMULATOR_BITASBOOL +typedef bit bit_as_bool; +`endif + +(* SC_MODULE_EXPORT *) +module design_1_xlconstant_0_3 ( + output bit [23 : 0 ] dout +); +endmodule +`endif + +`ifdef XCELIUM +(* XMSC_MODULE_EXPORT *) +module design_1_xlconstant_0_3 (dout) +(* integer foreign = "SystemC"; +*); + output wire [23 : 0 ] dout; +endmodule +`endif + +`ifdef RIVIERA +(* SC_MODULE_EXPORT *) +module design_1_xlconstant_0_3 (dout) + output wire [23 : 0 ] dout; +endmodule +`endif + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/xlconstant_v1_1_7.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/xlconstant_v1_1_7.h new file mode 100644 index 0000000..434d287 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/xlconstant_v1_1_7.h @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _xlconstant_v1_1_7_H_ +#define _xlconstant_v1_1_7_H_ + +#include "systemc.h" +template +SC_MODULE(xlconstant_v1_1_7) { + public: + sc_out< sc_bv > dout; + void init() { + dout.write(CONST_VAL); + } + SC_CTOR(xlconstant_v1_1_7) { + SC_METHOD(init); + } +}; + +#endif diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/synth/design_1_xlconstant_0_3.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/synth/design_1_xlconstant_0_3.v new file mode 100644 index 0000000..796ce2a --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/synth/design_1_xlconstant_0_3.v @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 7 + +(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2020.2" *) +(* CHECK_LICENSE_TYPE = "design_1_xlconstant_0_3,xlconstant_v1_1_7_xlconstant,{}" *) +(* CORE_GENERATION_INFO = "design_1_xlconstant_0_3,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=24,CONST_VAL=0x000001}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlconstant_0_3 ( + dout +); + +output wire [23 : 0] dout; + + xlconstant_v1_1_7_xlconstant #( + .CONST_WIDTH(24), + .CONST_VAL(24'H000001) + ) inst ( + .dout(dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xml new file mode 100644 index 0000000..b939c0f --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xml @@ -0,0 +1,72 @@ + + + xilinx.com + customized_ip + design_1_xlconstant_1_0 + 1.0 + + + + dout + + out + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + CONST_WIDTH + Const Width + 24 + + + CONST_VAL + Const Val + 0x000001 + + + + Gives a constant signed value. + + + Component_Name + design_1_xlconstant_1_0 + + + CONST_WIDTH + Const Width + 24 + + + CONST_VAL + Const Val + 1 + + + + + Constant + 7 + + + + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xml new file mode 100644 index 0000000..ce87e59 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xml @@ -0,0 +1,236 @@ + + + xilinx.com + customized_ip + design_1_xlslice_0_0 + 1.0 + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + xlslice_v1_0_2_xlslice + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:2b317e54 + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + design_1_xlslice_0_0 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:2b317e54 + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + xlslice_v1_0_2_xlslice + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Mon Apr 18 16:39:42 UTC 2022 + + + outputProductCRC + 9:c6ad224f + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:c6ad224f + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + design_1_xlslice_0_0 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jan 16 16:56:06 UTC 2024 + + + outputProductCRC + 9:c6ad224f + + + + + + + Din + + in + + 23 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + Dout + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + DIN_WIDTH + Din Width + 24 + + + DIN_FROM + Din From + 23 + + + DIN_TO + Din Down To + 23 + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v + verilogSource + USED_IN_ipstatic + xlslice_v1_0_2 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/design_1_xlslice_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_verilogsynthesis_view_fileset + + ../../ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v + verilogSource + xlslice_v1_0_2 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/design_1_xlslice_0_0.v + verilogSource + xil_defaultlib + + + + Slices a number of bits off of Din input. dout = din[from_position : to_position] + + + Component_Name + design_1_xlslice_0_0 + + + DIN_TO + Din Down To + 23 + + + DIN_FROM + Din From + 23 + + + DIN_WIDTH + Din Width + 24 + + + DOUT_WIDTH + Dout Width + 1 + + + + + Slice + 2 + + + + + + + + + 2020.2 + + + + + + + diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v new file mode 100644 index 0000000..c5f22b1 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v @@ -0,0 +1,72 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlslice:1.0 +// IP Revision: 2 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlslice_0_0 ( + Din, + Dout +); + +input wire [23 : 0] Din; +output wire [0 : 0] Dout; + + xlslice_v1_0_2_xlslice #( + .DIN_WIDTH(24), + .DIN_FROM(23), + .DIN_TO(23) + ) inst ( + .Din(Din), + .Dout(Dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/synth/design_1_xlslice_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/synth/design_1_xlslice_0_0.v new file mode 100644 index 0000000..a9d492d --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/synth/design_1_xlslice_0_0.v @@ -0,0 +1,73 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlslice:1.0 +// IP Revision: 2 + +(* X_CORE_INFO = "xlslice_v1_0_2_xlslice,Vivado 2020.2" *) +(* CHECK_LICENSE_TYPE = "design_1_xlslice_0_0,xlslice_v1_0_2_xlslice,{}" *) +(* CORE_GENERATION_INFO = "design_1_xlslice_0_0,xlslice_v1_0_2_xlslice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=24,DIN_FROM=23,DIN_TO=23}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xlslice_0_0 ( + Din, + Dout +); + +input wire [23 : 0] Din; +output wire [0 : 0] Dout; + + xlslice_v1_0_2_xlslice #( + .DIN_WIDTH(24), + .DIN_FROM(23), + .DIN_TO(23) + ) inst ( + .Din(Din), + .Dout(Dout) + ); +endmodule diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xml new file mode 100644 index 0000000..ff6931d --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xml @@ -0,0 +1,106 @@ + + + xilinx.com + customized_ip + design_1_xlslice_0_0 + 1.0 + + + + Din + + in + + 23 + 0 + + + + std_logic_vector + dummy_view + + + + + + Dout + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + DIN_WIDTH + Din Width + 24 + + + DIN_FROM + Din From + 23 + + + DIN_TO + Din Down To + 23 + + + + Slices a number of bits off of Din input. dout = din[from_position : to_position] + + + Component_Name + design_1_xlslice_0_0 + + + DIN_TO + Din Down To + 23 + + + DIN_FROM + Din From + 23 + + + DIN_WIDTH + Din Width + 24 + + + DOUT_WIDTH + Dout Width + 1 + + + + + Slice + 2 + + + + + + + + + 2020.2 + + + + + + + -- cgit v1.2.3