From 3d81cfe9c1028ae989f580e42aad0414081b5e7c Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Sun, 18 May 2025 14:07:21 -0400 Subject: Batman --- .../bd/mref/affhexPmodSSD_v3/component.xml | 215 +++++++++++++++++++++ .../xgui/affhexPmodSSD_v3_v1_0.tcl | 25 +++ 2 files changed, 240 insertions(+) create mode 100644 pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/component.xml create mode 100644 pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/xgui/affhexPmodSSD_v3_v1_0.tcl (limited to 'pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3') diff --git a/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/component.xml new file mode 100644 index 0000000..4889a41 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/component.xml @@ -0,0 +1,215 @@ + + + xilinx.com + module_ref + affhexPmodSSD_v3 + 1.0 + + + reset + + + + + + + RST + + + reset + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + affhexPmodSSD_v3 + + + viewChecksum + b762c3ee + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + affhexPmodSSD_v3 + + + viewChecksum + b762c3ee + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + + + clk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reset + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + DA + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_btn + + in + + 3 + 0 + + + + STD_LOGIC_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + JPmod + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + const_CLK_Hz + Const Clk Hz + 100000000 + + + + + + xilinx_xpgui_view_fileset + + xgui/affhexPmodSSD_v3_v1_0.tcl + tclSource + CHECKSUM_e6d8f77e + XGUI_VERSION_2 + + + + xilinx.com:module_ref:affhexPmodSSD_v3:1.0 + + + const_CLK_Hz + Const Clk Hz + 100000000 + + + Component_Name + affhexPmodSSD_v3_v1_0 + + + + + + zynq + + + /UserIP + + affhexPmodSSD_v3_v1_0 + level_1 + module_ref + + IPI + + 1 + 2022-01-24T13:37:08Z + + + 2020.2 + + + diff --git a/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/xgui/affhexPmodSSD_v3_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/xgui/affhexPmodSSD_v3_v1_0.tcl new file mode 100644 index 0000000..908e4b1 --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/xgui/affhexPmodSSD_v3_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "const_CLK_Hz" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.const_CLK_Hz { PARAM_VALUE.const_CLK_Hz } { + # Procedure called to update const_CLK_Hz when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.const_CLK_Hz { PARAM_VALUE.const_CLK_Hz } { + # Procedure called to validate const_CLK_Hz + return true +} + + +proc update_MODELPARAM_VALUE.const_CLK_Hz { MODELPARAM_VALUE.const_CLK_Hz PARAM_VALUE.const_CLK_Hz } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.const_CLK_Hz}] ${MODELPARAM_VALUE.const_CLK_Hz} +} + -- cgit v1.2.3