From 3d81cfe9c1028ae989f580e42aad0414081b5e7c Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Sun, 18 May 2025 14:07:21 -0400 Subject: Batman --- .../sim_scripts/design_1/xsim/README.txt | 49 +++++++++++++ .../sim_scripts/design_1/xsim/cmd.tcl | 12 ++++ .../design_1/xsim/design_1_xlconstant_0_0.h | 65 +++++++++++++++++ .../design_1/xsim/design_1_xlconstant_0_1.h | 65 +++++++++++++++++ .../design_1/xsim/design_1_xlconstant_0_2.h | 65 +++++++++++++++++ .../design_1/xsim/design_1_xlconstant_0_3.h | 65 +++++++++++++++++ .../sim_scripts/design_1/xsim/file_info.txt | 28 ++++++++ .../sim_scripts/design_1/xsim/glbl.v | 84 ++++++++++++++++++++++ .../sim_scripts/design_1/xsim/vhdl.prj | 23 ++++++ .../sim_scripts/design_1/xsim/vlog.prj | 12 ++++ .../sim_scripts/design_1/xsim/xlconstant_v1_1_7.h | 69 ++++++++++++++++++ 11 files changed, 537 insertions(+) create mode 100644 pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/README.txt create mode 100644 pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/cmd.tcl create mode 100644 pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_0.h create mode 100644 pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_1.h create mode 100644 pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_2.h create mode 100644 pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_3.h create mode 100644 pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/file_info.txt create mode 100644 pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/glbl.v create mode 100644 pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vhdl.prj create mode 100644 pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vlog.prj create mode 100644 pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/xlconstant_v1_1_7.h (limited to 'pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim') diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/README.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/README.txt new file mode 100644 index 0000000..9d37c1d --- /dev/null +++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Jan 16 11:48:38 -0500 2024 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./design_1.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './design_1.sh' script. + +./design_1.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./design_1.sh -noclean_files + +For more information on the script, please type './design_1.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/cmd.tcl b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/cmd.tcl new file mode 100644 index 0000000..05f1b4f --- /dev/null +++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_0.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_0.h new file mode 100644 index 0000000..f1321c6 --- /dev/null +++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_0.h @@ -0,0 +1,65 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _design_1_xlconstant_0_0_H_ +#define _design_1_xlconstant_0_0_H_ + +#include "xlconstant_v1_1_7.h" +#include "systemc.h" +class design_1_xlconstant_0_0 : public sc_module { + public: +xlconstant_v1_1_7<8,0> mod; + sc_out< sc_bv<8> > dout; +design_1_xlconstant_0_0 (sc_core::sc_module_name name); + }; + +#endif diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_1.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_1.h new file mode 100644 index 0000000..c1a0432 --- /dev/null +++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_1.h @@ -0,0 +1,65 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _design_1_xlconstant_0_1_H_ +#define _design_1_xlconstant_0_1_H_ + +#include "xlconstant_v1_1_7.h" +#include "systemc.h" +class design_1_xlconstant_0_1 : public sc_module { + public: +xlconstant_v1_1_7<1,1> mod; + sc_out< sc_bv<1> > dout; +design_1_xlconstant_0_1 (sc_core::sc_module_name name); + }; + +#endif diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_2.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_2.h new file mode 100644 index 0000000..f81da77 --- /dev/null +++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_2.h @@ -0,0 +1,65 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _design_1_xlconstant_0_2_H_ +#define _design_1_xlconstant_0_2_H_ + +#include "xlconstant_v1_1_7.h" +#include "systemc.h" +class design_1_xlconstant_0_2 : public sc_module { + public: +xlconstant_v1_1_7<1,1> mod; + sc_out< sc_bv<1> > dout; +design_1_xlconstant_0_2 (sc_core::sc_module_name name); + }; + +#endif diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_3.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_3.h new file mode 100644 index 0000000..58f2af3 --- /dev/null +++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_3.h @@ -0,0 +1,65 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _design_1_xlconstant_0_3_H_ +#define _design_1_xlconstant_0_3_H_ + +#include "xlconstant_v1_1_7.h" +#include "systemc.h" +class design_1_xlconstant_0_3 : public sc_module { + public: +xlconstant_v1_1_7<24,1> mod; + sc_out< sc_bv<24> > dout; +design_1_xlconstant_0_3 (sc_core::sc_module_name name); + }; + +#endif diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/file_info.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/file_info.txt new file mode 100644 index 0000000..b8b4e38 --- /dev/null +++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/file_info.txt @@ -0,0 +1,28 @@ +design_1_compteur_nbits_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd, +design_1_mef_decod_i2s_v1b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd, +design_1_reg_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd, +design_1_reg_24b_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd, +design_1_reg_dec_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd, +design_1_compteur_nbits_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd, +design_1_mef_cod_i2s_vsb_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd, +design_1_mux2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd, +design_1_reg_dec_24b_fd_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd, +design_1_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v, +design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v, +design_1_xlconstant_0_1.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v, +design_1_xlslice_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v, +design_1_affhexPmodSSD_v3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd, +design_1_calcul_param_1_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd, +design_1_calcul_param_2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd, +design_1_calcul_param_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd, +design_1_module_commande_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd, +design_1_mux4_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd, +design_1_mux4_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd, +design_1_sig_fct_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd, +design_1_sig_fct_sat_dure_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd, +design_1_sig_fct_sat_dure_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd, +design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v, +design_1_xlconstant_0_2.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v, +design_1_xlconstant_0_3.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v, +design_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/sim/design_1.vhd, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/glbl.v b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vhdl.prj b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vhdl.prj new file mode 100644 index 0000000..f281bb1 --- /dev/null +++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vhdl.prj @@ -0,0 +1,23 @@ +vhdl xil_defaultlib \ +"../../../bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd" \ +"../../../bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd" \ +"../../../bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd" \ +"../../../bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd" \ +"../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd" \ +"../../../bd/design_1/sim/design_1.vhd" \ + +nosort diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vlog.prj b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vlog.prj new file mode 100644 index 0000000..4ba9ab7 --- /dev/null +++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vlog.prj @@ -0,0 +1,12 @@ +verilog xil_defaultlib \ +"../../../bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v" \ +"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \ +"../../../bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v" \ +"../../../bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v" \ +"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \ +"../../../bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v" \ +"../../../bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/xlconstant_v1_1_7.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/xlconstant_v1_1_7.h new file mode 100644 index 0000000..434d287 --- /dev/null +++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/xlconstant_v1_1_7.h @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:xlconstant:1.1 +// IP Revision: 1 + +#ifndef _xlconstant_v1_1_7_H_ +#define _xlconstant_v1_1_7_H_ + +#include "systemc.h" +template +SC_MODULE(xlconstant_v1_1_7) { + public: + sc_out< sc_bv > dout; + void init() { + dout.write(CONST_VAL); + } + SC_CTOR(xlconstant_v1_1_7) { + SC_METHOD(init); + } +}; + +#endif -- cgit v1.2.3