From 3d81cfe9c1028ae989f580e42aad0414081b5e7c Mon Sep 17 00:00:00 2001 From: Benjamin Chausse Date: Sun, 18 May 2025 14:07:21 -0400 Subject: Batman --- .../constrs_1/imports/new/circuit_tr_signal.xdc | 318 +++++++++++++++++++++ 1 file changed, 318 insertions(+) create mode 100644 pb_logique_seq.srcs/constrs_1/imports/new/circuit_tr_signal.xdc (limited to 'pb_logique_seq.srcs/constrs_1/imports/new') diff --git a/pb_logique_seq.srcs/constrs_1/imports/new/circuit_tr_signal.xdc b/pb_logique_seq.srcs/constrs_1/imports/new/circuit_tr_signal.xdc new file mode 100644 index 0000000..78f6d59 --- /dev/null +++ b/pb_logique_seq.srcs/constrs_1/imports/new/circuit_tr_signal.xdc @@ -0,0 +1,318 @@ +## circuit_tr_signal.xdc +## This file is a general .xdc for the Zybo Z7 Rev. B +## It is compatible with the Zybo Z7-20 and Zybo Z7-10 +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Adaptation projet demo_codec_zybo +## D. Dalle, octobre 2018, janvier 2019 +## ref Using Constraints 78 +# UG903 (v2018.2) June 6, 2018 +## + +##Clock signal +set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk +create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }]; + + +##Switches (master) +#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0] +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2] +#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3] + +##Switches (demo_voltm_zybo, demo_codec_zybo) +set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { i_sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0] +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { i_sw[1] }]; #IO_L24P_T3_34 Sch=sw[1] +set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { i_sw[2] }]; #IO_L4N_T0_34 Sch=sw[2] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { i_sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3] + +###Switches (ThermoBin) +#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { i_sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0] +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { i_sw[1] }]; #IO_L24P_T3_34 Sch=sw[1] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { i_sw[2] }]; #IO_L4N_T0_34 Sch=sw[2] +#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { i_sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3] + +##Buttons (master) +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0] +#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1] +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2] +#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3] + +##Buttons (demo_voltm_zybo) +set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { i_btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0] +set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { i_btn[1] }]; #IO_L24N_T3_34 Sch=btn[1] +set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { i_btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2] +set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { i_btn[3] }]; #IO_L7P_T1_34 Sch=btn[3] + +###Buttons (ThermoBin) +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { i_btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0] +#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { i_btn[1] }]; #IO_L24N_T3_34 Sch=btn[1] +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { i_btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2] +#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { i_btn[3] }]; #IO_L7P_T1_34 Sch=btn[3] + + +##LEDs (master) +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0] +#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1] +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3] + +##LEDs (demo_voltm_zybo, demo_codec_zybo_v1) +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { o_led[0] }]; #IO_L23P_T3_35 Sch=led[0] +set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_L23N_T3_35 Sch=led[1] +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { o_led[2] }]; #IO_0_35 Sch=led[2] +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { o_led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3] + +###LEDs (ThermoBin) +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { o_led[0] }]; #IO_L23P_T3_35 Sch=led[0] +#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_L23N_T3_35 Sch=led[1] +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { o_led[2] }]; #IO_0_35 Sch=led[2] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { o_led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3] + +##RGB LED 5 (Zybo Z7-20 only) +#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r +#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g +#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b + +##RGB LED 6 (master) +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b + +##RGB LED 6 (demo_codec_zybo_v4) +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { o_temoin1Hz }]; #IO_L18P_T2_34 Sch=led6_r +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { o_led6_r }]; #IO_L18P_T2_34 Sch=led6_r +set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { o_led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b + + +##Audio Codec (master) +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk +#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc +#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda + +##Audio Codec (demo_codec_zybo_v1) +set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { o_ac_bclk }]; #IO_0_34 Sch=ac_bclk +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { o_ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { o_ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { o_ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat +set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { o_ac_pblrc }]; #IO_25_34 Sch=ac_pblrc +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { i_ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat +set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { o_ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc +set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { io_ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl +set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { io_ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda +##Audio Codec/external EEPROM IIC bus +##set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports iic_scl_io]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL +##set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports iic_sda_io]; #IO_L23P_T3_34 Sch=AC_SDA + + +######## zybo-z7-dma.xdc +###I2S Audio Codec +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK +#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC +#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC +###Audio Codec/external EEPROM IIC bus +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports iic_scl_io]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports iic_sda_io]; #IO_L23P_T3_34 Sch=AC_SDA + + +##Additional Ethernet signals +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b + + +##USB-OTG over-current detect pin +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc + + +##Fan (Zybo Z7-20 only) +#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu + + +##HDMI RX +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p +#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0] +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0] +#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1] +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1] +#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2] +#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2] + +##HDMI RX CEC (Zybo Z7-20 only) +#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec + + +##HDMI TX +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p +#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0] +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0] +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1] +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1] +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2] +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2] + +##HDMI TX CEC +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec + +##Pmod Header JA (XADC), (MASTER), +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N + +#demo_sync_zybo demo_codec_zybo +###Pmod Header JA (demo_sync_zybo, demo_codec_zybo branchement: PmodSSD), # pmod8LD +set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p # pmod haut +set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P # pmod haut +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P # pmod haut +set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P # pmod haut +set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N # pmod bas +set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N # pmod bas +set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N # pmod bas +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N # pmod bas + + +###Pmod Header JB (Zybo Z7-20 only) +#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1] +#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1] +#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2] +#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2] +#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3] +#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3] +#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4] +#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4] + +###Pmod Header JC (master) +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1] +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1] +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2] +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2] +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3] +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3] +#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4] +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4] + + +##Pmod Header JC (demo_sync_zybo: compteur , demo_codec_zybo : ) +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[0] }]; #IO_L10P_T1_34 Sch=jc_p[1] # pmod haut +set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[1] }]; #IO_L10N_T1_34 Sch=jc_n[1] # pmod haut +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[2] }]; #IO_L1P_T0_34 Sch=jc_p[2] # pmod haut +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[3] }]; #IO_L1N_T0_34 Sch=jc_n[2] # pmod haut +set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[4] }]; #IO_L8P_T1_34 Sch=jc_p[3] # pmod bas +set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[5] }]; #IO_L8N_T1_34 Sch=jc_n[3] # pmod bas +set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[6] }]; #IO_L2P_T0_34 Sch=jc_p[4] # pmod bas +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { o_pmodled[7] }]; #IO_L2N_T0_34 Sch=jc_n[4] # pmod bas + + + +##Pmod Header JD (master) +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1] +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2] +#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2] +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3] +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3] +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4] +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4] + +# #Pmod Header JD (demo_codec_zybo: signaux de tests version 3b ) +# set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { DIO[0] }]; #IO_L5P_T0_34 Sch=jd_p[1] # # pmod haut +# set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { DIO[1] }]; #IO_L5N_T0_34 Sch=jd_n[1] # # pmod haut +# set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { DIO[2] }]; #IO_L6P_T0_34 Sch=jd_p[2] # # pmod haut +# set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { DIO[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2] # # pmod haut +# set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { DIO[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3] ## pmod bas +# set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { DIO[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3] ## pmod bas +# set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { DIO[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4] ## pmod bas +# set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { DIO[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4] ## pmod bas + + + +# # Pmod Header JE ((demo_codec_zybo_v3b: signaux de tests revision 9 janvier 2019 ) rev v3 ) +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { DIO[8] }]; #IO_L4P_T0_34 Sch=je[1] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { DIO[9] }]; #IO_L18N_T2_34 Sch=je[2] +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { DIO[10] }]; #IO_25_35 Sch=je[3] +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DIO[11] }]; #IO_L19P_T3_35 Sch=je[4] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { DIO[12] }]; #IO_L3N_T0_DQS_34 Sch=je[7] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { DIO[13] }]; #IO_L9N_T1_DQS_34 Sch=je[8] +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { DIO[14] }]; #IO_L20P_T3_34 Sch=je[9] +#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { DIO[15] }]; #IO_L7N_T1_34 Sch=je[10] + + +##Pmod Header JE (master) +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2] +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3] +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8] +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9] +#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10] + + + +##Pcam MIPI CSI-2 Connector +## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk +#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p] +#set_property INTERNAL_VREF 0.6 [get_iobanks 35] +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0] +#set_property -dict { PACKAGE_PIN L19 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0] +#set_property -dict { PACKAGE_PIN L20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1] +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1] +#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p +#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0] +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0] +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1] +#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1] +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda + + +##Unloaded Crypto Chip SWI (for future use) +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda + + +##Unconnected Pins (Zybo Z7-20 only) +#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13 +#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13 +#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13 +#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13 +#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13 +#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13 +#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13 +#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13 +#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13 +#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13 +#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13 +#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13 + + -- cgit v1.2.3