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b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.xci new file mode 100644 index 0000000..793a998 --- /dev/null +++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.xci @@ -0,0 +1,49 @@ + + + xilinx.com + xci + unknown + 1.0 + + + design_1_calcul_param_2_0_0 + + + 0 + ACTIVE_LOW + design_1_calcul_param_2_0_0 + zynq + digilentinc.com:zybo-z7-10:part0:1.0 + + xc7z010 + clg400 + VHDL + + MIXED + -1 + + + TRUE + TRUE + IP_Integrator + 1 + TRUE + ../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0 + + ../../ipshared + 2020.2 + OOC_HIERARCHICAL + + + + + + + + + + + + + + diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/design_1_calcul_param_3_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/design_1_calcul_param_3_0_0.xci new file mode 100644 index 0000000..7caf920 --- /dev/null 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OOC_HIERARCHICAL + + + + + + + + + + + + + + + diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xci new file mode 100644 index 0000000..6a2380a --- /dev/null +++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xci @@ -0,0 +1,53 @@ + + + xilinx.com + xci + unknown + 1.0 + + + design_1_mef_cod_i2s_vsb_0_0 + + + 0 + ACTIVE_LOW + 0 + ACTIVE_LOW + design_1_mef_cod_i2s_vsb_0_0 + zynq + + + xc7z010 + clg400 + VHDL + + MIXED + -1 + + + TRUE + TRUE + IP_Integrator + 1 + TRUE + ../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1 + + ../../ipshared + 2020.2 + OOC_HIERARCHICAL + + + + + + + + + + + + + + + diff --git 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b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_module_commande_0_0/design_1_module_commande_0_0.xci new file mode 100644 index 0000000..a7debdd --- /dev/null +++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_module_commande_0_0/design_1_module_commande_0_0.xci @@ -0,0 +1,68 @@ + + + xilinx.com + xci + unknown + 1.0 + + + design_1_module_commande_0_0 + + + + + design_1_clk_100MHz + 100000000 + 0 + 0 + 0.000 + 0 + ACTIVE_LOW + "0" + 4 + design_1_module_commande_0_0 + "0" + 4 + zynq + digilentinc.com:zybo-z7-10:part0:1.0 + + xc7z010 + clg400 + VHDL + + MIXED + -1 + + + TRUE + TRUE + IP_Integrator + 1 + TRUE + ../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0 + + ../../ipshared + 2020.2 + OOC_HIERARCHICAL + + + + + + + + + + + + + + + + + + + + diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.xci new 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a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xci new file mode 100644 index 0000000..5821b63 --- /dev/null +++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xci @@ -0,0 +1,48 @@ + + + xilinx.com + xci + unknown + 1.0 + + + design_1_xlconstant_1_0 + + + 0x000001 + 24 + 1 + 24 + design_1_xlconstant_1_0 + zynq + + + xc7z010 + clg400 + VHDL + + MIXED + -1 + + + TRUE + TRUE + IP_Integrator + 7 + TRUE + ../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_1_0 + + ../../ipshared + 2020.2 + GLOBAL + + + + + + + + + + + diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xci new file mode 100644 index 0000000..0bf5c35 --- /dev/null +++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xci @@ -0,0 +1,54 @@ + + + xilinx.com + xci + unknown + 1.0 + + + design_1_xlslice_0_0 + + + 23 + 23 + 24 + design_1_xlslice_0_0 + 23 + 23 + 24 + 1 + zynq + digilentinc.com:zybo-z7-10:part0:1.0 + + xc7z010 + clg400 + VHDL + + MIXED + -1 + + + TRUE + TRUE + IP_Integrator + 2 + TRUE + ../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0 + + ../../ipshared + 2020.2 + GLOBAL + + + + + + + + + + + + + + diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xci new file mode 100644 index 0000000..cc800da --- /dev/null +++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xci @@ -0,0 +1,54 @@ + + + xilinx.com + xci + unknown + 1.0 + + + design_1_xlslice_0_0 + + + 23 + 23 + 24 + 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