From 3d81cfe9c1028ae989f580e42aad0414081b5e7c Mon Sep 17 00:00:00 2001
From: Benjamin Chausse <benjamin@chausse.xyz>
Date: Sun, 18 May 2025 14:07:21 -0400
Subject: Batman

---
 pb_logique_seq.srcs/sources_1/imports/new/mux4.vhd | 65 ++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 pb_logique_seq.srcs/sources_1/imports/new/mux4.vhd

(limited to 'pb_logique_seq.srcs/sources_1/imports/new/mux4.vhd')

diff --git a/pb_logique_seq.srcs/sources_1/imports/new/mux4.vhd b/pb_logique_seq.srcs/sources_1/imports/new/mux4.vhd
new file mode 100644
index 0000000..4e46dbc
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/mux4.vhd
@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 11/18/2021 11:51:08 AM
+-- Design Name: 
+-- Module Name: mux4 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity mux4 is
+    Generic ( input_length : integer := 24 );
+    Port ( input0 : in STD_LOGIC_VECTOR (input_length-1 downto 0);
+           input1 : in STD_LOGIC_VECTOR (input_length-1 downto 0);
+           input2 : in STD_LOGIC_VECTOR (input_length-1 downto 0);
+           input3 : in STD_LOGIC_VECTOR (input_length-1 downto 0);
+           sel : in STD_LOGIC_VECTOR (1 downto 0);
+           output0 : out STD_LOGIC_VECTOR (input_length-1 downto 0));
+end mux4;
+
+architecture Behavioral of mux4 is
+
+begin
+
+process(sel, input0, input1, input2, input3)
+begin
+  case sel is
+                 when "00" =>
+                     output0 <= input0;
+                 when   "01" =>
+                     output0 <= input1;
+                 when   "10"  =>
+                     output0 <= input2;
+                 when    "11"  =>
+                     output0 <= input3;
+                 when  others  =>
+                     output0 <= input0;
+                 end case;
+end process;
+
+
+end Behavioral;
-- 
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