xilinx.com module_ref affhexPmodSSD_v3 1.0 reset RST reset clk CLK clk ASSOCIATED_RESET reset xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL affhexPmodSSD_v3 viewChecksum b762c3ee xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL affhexPmodSSD_v3 viewChecksum b762c3ee xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset clk in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DA in 7 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_btn in 3 0 STD_LOGIC_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation JPmod out 7 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation const_CLK_Hz Const Clk Hz 100000000 xilinx_xpgui_view_fileset xgui/affhexPmodSSD_v3_v1_0.tcl tclSource CHECKSUM_e6d8f77e XGUI_VERSION_2 xilinx.com:module_ref:affhexPmodSSD_v3:1.0 const_CLK_Hz Const Clk Hz 100000000 Component_Name affhexPmodSSD_v3_v1_0 zynq /UserIP affhexPmodSSD_v3_v1_0 level_1 module_ref IPI 1 2022-01-24T13:37:08Z 2020.2