xilinx.com module_ref compteur_nbits 1.0 reset RST reset clk CLK clk ASSOCIATED_RESET reset xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL compteur_nbits viewChecksum 249e7abe xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL compteur_nbits viewChecksum 249e7abe xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_val_cpt out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nbits Nbits 8 xilinx_xpgui_view_fileset xgui/compteur_nbits_v1_0.tcl tclSource CHECKSUM_912d28ee XGUI_VERSION_2 xilinx.com:module_ref:compteur_nbits:1.0 nbits Nbits 8 Component_Name compteur_nbits_v1_0 zynq /UserIP compteur_nbits_v1_0 level_1 module_ref IPI 1 2022-01-24T13:37:09Z 2020.2