xilinx.com module_ref mef_cod_i2s_vsb 1.0 i_reset RST i_reset o_cpt_bit_reset RST o_cpt_bit_reset xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL mef_cod_i2s_vsb viewChecksum 139c27c1 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL mef_cod_i2s_vsb viewChecksum 139c27c1 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset i_bclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_lrc in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_cpt_bits in 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_bit_enable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_load_left out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_load_right out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_cpt_bit_reset out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation xilinx_xpgui_view_fileset xgui/mef_cod_i2s_vsb_v1_0.tcl tclSource CHECKSUM_f64a5dae XGUI_VERSION_2 xilinx.com:module_ref:mef_cod_i2s_vsb:1.0 Component_Name mef_cod_i2s_vsb_v1_0 zynq /UserIP mef_cod_i2s_vsb_v1_0 level_1 module_ref IPI 1 2022-01-24T13:37:09Z 2020.2