xilinx.com module_ref module_commande 1.0 o_reset RST o_reset clk CLK clk xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL module_commande viewChecksum 2df8a718 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL module_commande viewChecksum 2df8a718 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_reset out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_btn in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_sw in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_btn_cd out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_selection_fct out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_selection_par out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nbtn Nbtn 4 mode_simulation Mode Simulation "0" xilinx_xpgui_view_fileset xgui/module_commande_v1_0.tcl tclSource CHECKSUM_98c0d650 XGUI_VERSION_2 xilinx.com:module_ref:module_commande:1.0 nbtn Nbtn 4 mode_simulation Mode Simulation "0" Component_Name module_commande_v1_0 zynq /UserIP module_commande_v1_0 level_1 module_ref IPI 1 2024-01-16T16:44:59Z 2020.2