xilinx.com module_ref mux2 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL mux2 viewChecksum d3169f7e xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL mux2 viewChecksum d3169f7e xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset sel in 1 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation input1 in 23 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation input2 in 23 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation output0 out 23 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation input_length Input Length 24 xilinx_xpgui_view_fileset xgui/mux2_v1_0.tcl tclSource CHECKSUM_6aef23ef XGUI_VERSION_2 xilinx.com:module_ref:mux2:1.0 input_length Input Length 24 Component_Name mux2_v1_0 zynq /UserIP mux2_v1_0 level_1 module_ref IPI 1 2022-01-24T13:37:10Z 2020.2