xilinx.com module_ref mux4 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL mux4 viewChecksum 35010ed3 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL mux4 viewChecksum 35010ed3 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset input0 in 23 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation input1 in 23 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation input2 in 23 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation input3 in 23 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sel in 1 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation output0 out 23 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation input_length Input Length 24 xilinx_xpgui_view_fileset xgui/mux4_v1_0.tcl tclSource CHECKSUM_6aef23ef XGUI_VERSION_2 xilinx.com:module_ref:mux4:1.0 input_length Input Length 24 Component_Name mux4_v1_0 zynq /UserIP mux4_v1_0 level_1 module_ref IPI 1 2022-01-24T13:37:10Z 2020.2