xilinx.com module_ref reg_24b 1.0 i_reset RST i_reset i_clk CLK i_clk ASSOCIATED_RESET i_reset xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL reg_24b viewChecksum 34a41093 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL reg_24b viewChecksum 34a41093 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset i_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_dat in 23 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_dat out 23 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation xilinx_xpgui_view_fileset xgui/reg_24b_v1_0.tcl tclSource CHECKSUM_f64a5dae XGUI_VERSION_2 xilinx.com:module_ref:reg_24b:1.0 Component_Name reg_24b_v1_0 zynq /UserIP reg_24b_v1_0 level_1 module_ref IPI 1 2022-01-24T13:37:10Z 2020.2