diff options
| -rw-r--r-- | pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd | 17 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd | 11 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/new/fct_2_3_tb.vhd | 8 |
3 files changed, 28 insertions, 8 deletions
diff --git a/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd index d05f1fa..9afc9f2 100644 --- a/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd +++ b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd @@ -54,7 +54,11 @@ architecture Behavioral of AppCombi_top_tb is o_led : out std_logic_vector (3 downto 0);
o_led6_r : out std_logic;
o_pmodled : out std_logic_vector (7 downto 0);
- ADCth : out std_logic_vector (11 downto 0)); -- Connecteur ADCth thermometrique
+ ADCth : out std_logic_vector (11 downto 0); -- Connecteur ADCth thermometrique
+ DEL1 : out std_logic; -- Carte thermometrique
+ DEL2 : out std_logic; -- Carte thermometrique
+ button_s1 : in std_logic; -- Carte thermometrique
+ button_s2 : in std_logic); -- Carte thermometrique
end component;
signal clk_sim : STD_LOGIC := '0';
@@ -66,6 +70,10 @@ architecture Behavioral of AppCombi_top_tb is signal btn_sim : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal cin_sim : STD_LOGIC := '0';
signal ADCth_sim : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
+ signal DEL1_sim : STD_LOGIC := '0';
+ signal DEL2_sim : STD_LOGIC := '0';
+ signal button_s1_sim : STD_LOGIC := '0';
+ signal button_s2_sim : STD_LOGIC := '0';
signal vecteur_test_sim : STD_LOGIC_VECTOR (13 downto 0) := (others => '0');
signal resultat_attendu : STD_LOGIC_VECTOR (4 downto 0) := "00000";
@@ -132,8 +140,11 @@ begin o_led => led_sim,
o_pmodled => pmodled_sim,
o_led6_r => led6_r_sim,
- ADCth => ADCth_sim);
-
+ ADCth => ADCth_sim,
+ DEL2 => DEL2_sim,
+ DEL1 => DEL1_sim,
+ button_s1 => button_s1_sim,
+ button_s2 => button_s2_sim);
-- Section banc de test
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd b/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd index d1513fa..a557145 100644 --- a/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd +++ b/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd @@ -42,6 +42,7 @@ architecture Behavioral of Fct_2_3 is signal shifted_once : STD_LOGIC_VECTOR(3 downto 0); signal shifted_twice : STD_LOGIC_VECTOR(3 downto 0); signal shifted_thrice : STD_LOGIC_VECTOR(3 downto 0); + signal carry_in : STD_LOGIC; signal carry_out : STD_LOGIC; signal added : STD_LOGIC_VECTOR(3 downto 0); @@ -60,11 +61,19 @@ begin shifted_twice <= '0' & shifted_once(3 downto 1); shifted_thrice <= '0' & shifted_twice(3 downto 1); + -- If we shifted 4 times... There's cases where the decimal point would cause a carry in to exist! + -- If we don't take that into account... the number 4 will NEVER show up! + -- Here's how to figure out if there can be a carry in + -- 1001 -> 0100,1, so index 0 is when it's shifted once + -- 1100 -> 0001,1 so index 2 is the deecimal when shifted 3 times. + -- If both are true, the addition should've made a carry in! + carry_in <= ADCbin(0) AND ADCbin(2); + -- Both are then added to give the result of the 2/3 multiplication (0.625) result : Add4Bits port map ( A => shifted_once, B => shifted_thrice, - C => '0', + C => carry_in, R => added, Rc => carry_out ); diff --git a/pb_APP_log_comb.srcs/sources_1/new/fct_2_3_tb.vhd b/pb_APP_log_comb.srcs/sources_1/new/fct_2_3_tb.vhd index 2d89a59..370c760 100644 --- a/pb_APP_log_comb.srcs/sources_1/new/fct_2_3_tb.vhd +++ b/pb_APP_log_comb.srcs/sources_1/new/fct_2_3_tb.vhd @@ -63,12 +63,12 @@ architecture Behavioral of fct_2_3_tb is -- res input "000" & "0000", -- 0 "000" & "0001", -- 1 - "001" & "0010", + "001" & "0010", "001" & "0011", - "010" & "0100", - "010" & "0101", + "010" & "0100", + "011" & "0101", "011" & "0110", -- 0011, 0000 - "011" & "0111", -- 0011, 0000 + "100" & "0111", -- 0011, 0000 "101" & "1000", -- 0100, 0001 "101" & "1001", -- 0100, 0001 "110" & "1010", |