3 files changed, 126 insertions, 30 deletions
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
index b00716e..5f99927 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
@@ -1,21 +1,21 @@
 ----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
+-- Company:
+-- Engineer:
+--
 -- Create Date: 04/30/2025 03:19:19 PM
--- Design Name: 
+-- Design Name:
 -- Module Name: Add1BitB - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
 -- Revision:
 -- Revision 0.01 - File Created
 -- Additional Comments:
--- 
+--
 ----------------------------------------------------------------------------------
 
 
@@ -41,7 +41,48 @@ end Add1BitB;
 
 architecture Behavioral of Add1BitB is
 
+  signal buf: STD_LOGIC_VECTOR(2 downto 0);
+
+begin
+
+Adder: process(X, Y, Ci) is
 begin
+  buf(0) <= X;
+  buf(1) <= Y;
+  buf(2) <= Ci;
+
+     case (buf) is
+      when "000" =>
+         O <= '0';
+         Co <= '0';
+      when "001" =>
+         O <= '1';
+         Co <= '0';
+      when "010" =>
+         O <= '1';
+         Co <= '0';
+      when "011" =>
+         O <= '0';
+         Co <= '1';
+      when "100" =>
+         O <= '1';
+         Co <= '0';
+      when "101" =>
+         O <= '0';
+         Co <= '1';
+      when "110" =>
+         O <= '0';
+         Co <= '1';
+      when "111" =>
+         O <= '1';
+         Co <= '1';
+      when others =>
+         O <= '0';
+         Co <= '0';
+   end case;
+
+end process Adder;
+
 
 
 end Behavioral;
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
index be2cf13..371d81b 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
@@ -1,21 +1,21 @@
 ----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
+-- Company:
+-- Engineer:
+--
 -- Create Date: 04/30/2025 03:19:19 PM
--- Design Name: 
+-- Design Name:
 -- Module Name: Add4Bits - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
 -- Revision:
 -- Revision 0.01 - File Created
 -- Additional Comments:
--- 
+--
 ----------------------------------------------------------------------------------
 
 
@@ -32,16 +32,71 @@ use IEEE.STD_LOGIC_1164.ALL;
 --use UNISIM.VComponents.all;
 
 entity Add4Bits is
-    Port ( X : in STD_LOGIC_VECTOR (0 to 3);
-           Y : in STD_LOGIC_VECTOR (0 to 3);
-           Ci : in STD_LOGIC;
-           O : out STD_LOGIC_VECTOR (0 to 3);
-           Co : out STD_LOGIC);
+    Port ( A : in STD_LOGIC_VECTOR (0 to 3);
+           B : in STD_LOGIC_VECTOR (0 to 3);
+           C : in STD_LOGIC;
+           R : out STD_LOGIC_VECTOR (0 to 3);
+           Rc : out STD_LOGIC);
 end Add4Bits;
 
 architecture Behavioral of Add4Bits is
 
+  signal bufA : STD_LOGIC;
+  signal bufB : STD_LOGIC;
+  signal bufC : STD_LOGIC;
+
+  component Add1BitA is
+    Port (
+     X : in STD_LOGIC;
+     Y : in STD_LOGIC;
+     Ci: in STD_LOGIC;
+     O : out STD_LOGIC;
+     Co: out STD_LOGIC
+  );
+  end component;
+
+  component Add1BitB is
+    Port (
+     X : in STD_LOGIC;
+     Y : in STD_LOGIC;
+     Ci: in STD_LOGIC;
+     O : out STD_LOGIC;
+     Co: out STD_LOGIC
+  );
+  end component;
+
 begin
 
+  first : Add1BitA port map (
+    X  => A(0),
+    Y  => B(0),
+    Ci => C,
+    O => R(0),
+    Co => bufA
+  );
+
+  sec : Add1BitA port map (
+    X  => A(1),
+    Y  => B(1),
+    Ci => bufA,
+    O => R(1),
+    Co => bufB
+  );
+
+  third : Add1BitB port map (
+    X  => A(2),
+    Y  => B(2),
+    Ci => bufB,
+    O => R(2),
+    Co => bufC
+  );
+
+  fourth : Add1BitB port map (
+    X  => A(3),
+    Y  => B(3),
+    Ci => bufC,
+    O => R(3),
+    Co => Rc
+  );
 
 end Behavioral;
diff --git a/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd b/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd
index 7f5148d..1ffef11 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd
@@ -1,6 +1,6 @@
 ----------------------------------------------------------------------------------
 -- Company:
--- Engineer:
+-- Engineer: BenTheMan
 --
 -- Create Date: 04/30/2025 01:11:03 PM
 -- Design Name: