diff options
| author | Benjamin Chausse <benjamin@chausse.xyz> | 2025-05-01 09:15:23 -0400 |
|---|---|---|
| committer | Benjamin Chausse <benjamin@chausse.xyz> | 2025-05-01 09:15:23 -0400 |
| commit | 0bfa029ee6c5bdbc6d5601b3200d7367fcea02ba (patch) | |
| tree | 2d6fd716e8ffd32c8df1151fb2ee229ab468ad0c | |
Batman
| -rw-r--r-- | .gitignore | 273 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd | 111 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_Top.vhd | 107 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_encodeur.vhd | 120 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_refreshPmod.vhd | 66 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/imports/src/synchro_module_v2.vhd | 130 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd | 49 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd | 47 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd | 47 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd | 54 | ||||
| -rw-r--r-- | pb_APP_log_comb.xpr | 283 |
11 files changed, 1287 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..9e1e38d --- /dev/null +++ b/.gitignore @@ -0,0 +1,273 @@ +######################################################################################################### +## This is an example .gitignore file for Vivado, please treat it as an example as +## it might not be complete. In addition, XAPP 1165 should be followed. +######################################################################################################### +######### +#Exclude all +######### +* +!*/ +!.gitignore +########################################################################### +## VIVADO +########################################################################### +######### +#Source files: +######### +#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. +!*.vhd +!*.v +!*.sv +!*.bd +!*.edif +######### +#IP files +######### +#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products +#.xci + .dcp: implementation possible but not re-synthesis +#*.xci(www.spiritconsortium.org) +!*.xci +#.xcix: Core container file +#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41) +!*.xcix +#*.dcp(checkpoint files) +!*.dcp +!*.vds +!*.pb +#All bd comments and layout coordinates are stored within .ui +!*.ui +!*.ooc +######### +#System Generator +######### +!*.mdl +!*.slx +!*.bxml +######### +#Simulation logic analyzer +######### +!*.wcfg +!*.coe +######### +#MIG +######### +!*.prj +!*.mem +######### +#Project files +######### +#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) +#Do NOT ignore *.xpr files +!*.xpr +#Include *.xml files for 2013.4 or earlier version +!*.xml +######### +#Constraint files +######### +#Do NOT ignore *.xdc files +!*.xdc +######### +#TCL - files +######### +!*.tcl +######### +#Journal - files +######### +!*.jou +######### +#Reports +######### +!*.rpt +!*.txt +!*.vdi +######### +#C-files +######### +!*.c +!*.h +!*.elf +!*.bmm +!*.xmp######################################################################################################### +## This is an example .gitignore file for Vivado, please treat it as an example as +## it might not be complete. In addition, XAPP 1165 should be followed. +######################################################################################################### +######### +#Exclude all +######### +* +!*/ +!.gitignore +########################################################################### +## VIVADO +########################################################################### +######### +#Source files: +######### +#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. +!*.vhd +!*.v +!*.sv +!*.bd +!*.edif +######### +#IP files +######### +#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products +#.xci + .dcp: implementation possible but not re-synthesis +#*.xci(www.spiritconsortium.org) +!*.xci +#.xcix: Core container file +#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41) +!*.xcix +#*.dcp(checkpoint files) +!*.dcp +!*.vds +!*.pb +#All bd comments and layout coordinates are stored within .ui +!*.ui +!*.ooc +######### +#System Generator +######### +!*.mdl +!*.slx +!*.bxml +######### +#Simulation logic analyzer +######### +!*.wcfg +!*.coe +######### +#MIG +######### +!*.prj +!*.mem +######### +#Project files +######### +#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) +#Do NOT ignore *.xpr files +!*.xpr +#Include *.xml files for 2013.4 or earlier version +!*.xml +######### +#Constraint files +######### +#Do NOT ignore *.xdc files +!*.xdc +######### +#TCL - files +######### +!*.tcl +######### +#Journal - files +######### +!*.jou +######### +#Reports +######### +!*.rpt +!*.txt +!*.vdi +######### +#C-files +######### +!*.c +!*.h +!*.elf +!*.bmm +!*.xmp######################################################################################################### +## This is an example .gitignore file for Vivado, please treat it as an example as +## it might not be complete. In addition, XAPP 1165 should be followed. +######################################################################################################### +######### +#Exclude all +######### +* +!*/ +!.gitignore +########################################################################### +## VIVADO +########################################################################### +######### +#Source files: +######### +#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. +!*.vhd +!*.v +!*.sv +!*.bd +!*.edif +######### +#IP files +######### +#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products +#.xci + .dcp: implementation possible but not re-synthesis +#*.xci(www.spiritconsortium.org) +!*.xci +#.xcix: Core container file +#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41) +!*.xcix +#*.dcp(checkpoint files) +!*.dcp +!*.vds +!*.pb +#All bd comments and layout coordinates are stored within .ui +!*.ui +!*.ooc +######### +#System Generator +######### +!*.mdl +!*.slx +!*.bxml +######### +#Simulation logic analyzer +######### +!*.wcfg +!*.coe +######### +#MIG +######### +!*.prj +!*.mem +######### +#Project files +######### +#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) +#Do NOT ignore *.xpr files +!*.xpr +#Include *.xml files for 2013.4 or earlier version +!*.xml +######### +#Constraint files +######### +#Do NOT ignore *.xdc files +!*.xdc +######### +#TCL - files +######### +!*.tcl +######### +#Journal - files +######### +!*.jou +######### +#Reports +######### +!*.rpt +!*.txt +!*.vdi +######### +#C-files +######### +!*.c +!*.h +!*.elf +!*.bmm +!*.xmp +######### +#Caches and runs +######### +*.cache/ +*.runs/ diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd new file mode 100644 index 0000000..0f939d4 --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd @@ -0,0 +1,111 @@ +---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version : 3.0
+-- Nomenclature : GRAMS
+-- Date : 21 Avril 2020
+-- Auteur(s) : Réjean Fontaine, Daniel Dalle, Marc-André Tétrault
+-- Technologies : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+-- peripheriques: Pmod8LD PmodSSD
+--
+-- Outils : vivado 2019.1 64 bits
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Circuit utilitaire pour le laboratoire et la problématique de logique combinatoire
+--
+---------------------------------------------------------------------------------------------
+-- À faire :
+-- Voir le guide de l'APP
+-- Insérer les modules additionneurs ("components" et "instances")
+--
+---------------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity AppCombi_top is
+ port (
+ i_btn : in std_logic_vector (3 downto 0); -- Boutons de la carte Zybo
+ i_sw : in std_logic_vector (3 downto 0); -- Interrupteurs de la carte Zybo
+ sysclk : in std_logic; -- horloge systeme
+ o_SSD : out std_logic_vector (7 downto 0); -- vers cnnecteur pmod afficheur 7 segments
+ o_led : out std_logic_vector (3 downto 0); -- vers DELs de la carte Zybo
+ o_led6_r : out std_logic; -- vers DEL rouge de la carte Zybo
+ o_pmodled : out std_logic_vector (7 downto 0) -- vers connecteur pmod 8 DELs
+ );
+end AppCombi_top;
+
+architecture BEHAVIORAL of AppCombi_top is
+
+ constant nbreboutons : integer := 4; -- Carte Zybo Z7
+ constant freq_sys_MHz : integer := 125; -- 125 MHz
+
+ signal d_s_1Hz : std_logic;
+ signal clk_5MHz : std_logic;
+ --
+ signal d_opa : std_logic_vector (3 downto 0):= "0000"; -- operande A
+ signal d_opb : std_logic_vector (3 downto 0):= "0000"; -- operande B
+ signal d_cin : std_logic := '0'; -- retenue entree
+ signal d_sum : std_logic_vector (3 downto 0):= "0000"; -- somme
+ signal d_cout : std_logic := '0'; -- retenue sortie
+ --
+ signal d_AFF0 : std_logic_vector (3 downto 0):= "0000";
+ signal d_AFF1 : std_logic_vector (3 downto 0):= "0000";
+
+
+ component synchro_module_v2 is
+ generic (const_CLK_syst_MHz: integer := freq_sys_MHz);
+ Port (
+ clkm : in STD_LOGIC; -- Entrée horloge maitre
+ o_CLK_5MHz : out STD_LOGIC; -- horloge divise utilise pour le circuit
+ o_S_1Hz : out STD_LOGIC -- Signal temoin 1 Hz
+ );
+ end component;
+
+ component septSegments_Top is
+ Port ( clk : in STD_LOGIC; -- horloge systeme, typique 100 MHz (preciser par le constante)
+ i_AFF0 : in STD_LOGIC_VECTOR (3 downto 0); -- donnee a afficher sur 8 bits : chiffre hexa position 1 et 0
+ i_AFF1 : in STD_LOGIC_VECTOR (3 downto 0); -- donnee a afficher sur 8 bits : chiffre hexa position 1 et 0
+ o_AFFSSD_Sim : out string(1 to 2);
+ o_AFFSSD : out STD_LOGIC_VECTOR (7 downto 0)
+ );
+ end component;
+
+
+begin
+
+ inst_synch : synchro_module_v2
+ generic map (const_CLK_syst_MHz => freq_sys_MHz)
+ port map (
+ clkm => sysclk,
+ o_CLK_5MHz => clk_5MHz,
+ o_S_1Hz => d_S_1Hz
+ );
+
+ inst_aff : septSegments_Top
+ port map (
+ clk => clk_5MHz,
+ -- donnee a afficher definies sur 8 bits : chiffre hexa position 1 et 0
+ i_AFF1 => d_AFF1,
+ i_AFF0 => d_AFF0,
+ o_AFFSSD_Sim => open, -- ne pas modifier le "open". Ligne pour simulations seulement.
+ o_AFFSSD => o_SSD -- sorties directement adaptees au connecteur PmodSSD
+ );
+
+
+ d_opa <= i_sw; -- operande A sur interrupteurs
+ d_opb <= i_btn; -- operande B sur boutons
+ d_cin <= '0'; -- la retenue d'entrée alterne 0 1 a 1 Hz
+
+ d_AFF0 <= d_sum(3 downto 0); -- Le resultat de votre additionneur affiché sur PmodSSD(0)
+ d_AFF1 <= '0' & '0' & '0' & d_Cout; -- La retenue de sortie affichée sur PmodSSD(1) (0 ou 1)
+ o_led6_r <= d_Cout; -- La led couleur représente aussi la retenue en sortie Cout
+ o_pmodled <= d_opa & d_opb; -- Les opérandes d'entrés reproduits combinés sur Pmod8LD
+ o_led (3 downto 0) <= '0' & '0' & '0' & d_S_1Hz; -- La LED0 sur la carte représente la retenue d'entrée
+
+
+end BEHAVIORAL;
+
+
diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_Top.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_Top.vhd new file mode 100644 index 0000000..3f72b23 --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_Top.vhd @@ -0,0 +1,107 @@ +---------------------------------------------------------------------------------------------
+-- circuit affhex_pmodssd.vhd
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version : 2.0
+-- Nomenclature : 0.8 GRAMS
+-- Date : revision 23 octobre 2018
+-- Auteur(s) : Réjean Fontaine, Daniel Dalle
+-- Technologies : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+-- Outils : vivado 2016.1 64 bits, vivado 2018.2
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Affichage sur module de 2 chiffes (7 segments) sur PmodSSD
+-- reference https://reference.digilentinc.com/reference/pmod/pmodssd/start
+-- PmodSSD™ Reference Manual Doc: 502-126 Digilent, Inc.
+--
+-- Revisions
+-- mise a jour D Dalle 22 octobre 2018 corrections, simplifications
+-- mise a jour D Dalle 15 octobre documentation affhex_pmodssd_sol_v0.vhd
+-- mise a jour D Dalle 12 septembre pour eviter l'usage d'une horloge interne
+-- mise a jour D Dalle 7 septembre, calcul des constantes.
+-- mise a jour D Dalle 5 septembre 2018, nom affhexPmodSSD, 6 septembre :division horloge
+-- module de commande le l'afficheur 2 segments 2 digits sur pmod
+-- Daniel Dalle revision pour sortir les signaux du connecteur Pmod directement
+-- Daniel Dalle 30 juillet 2018:
+-- revision pour une seule entre sur 8 bits affichee sur les deux chiffres Hexa
+--
+-- Creation selon affhex7segx4v3.vhd
+-- (Daniel Dalle, Réjean Fontaine Universite de Sherbrooke, Departement GEGI)
+-- 26 septembre 2011, revision 12 juin 2012, 25 janvier 2013, 7 mai 2015
+-- Contrôle de l'afficheur a sept segment (BASYS2 - NEXYS2)
+-- horloge 100MHz et diviseur interne
+---------------------------------------------------------------------------------------------
+-- À faire :
+--
+--
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity septSegments_Top is
+generic (const_CLK_MHz: integer := 100); -- horloge en MHz, typique 100 MHz
+ Port ( clk : in STD_LOGIC; -- horloge systeme, typique 100 MHz (preciser par le constante)
+ i_AFF0 : in STD_LOGIC_VECTOR (3 downto 0); -- donnee a afficher sur 4 bits : chiffre hexa position 0
+ i_AFF1 : in STD_LOGIC_VECTOR (3 downto 0); -- donnee a afficher sur 4 bits : chiffre hexa position 1
+ o_AFFSSD_Sim : out string(2 downto 1);
+ o_AFFSSD : out STD_LOGIC_VECTOR (7 downto 0)
+ );
+end septSegments_Top; -- sorties directement adaptees au connecteur PmodSSD
+
+architecture Behavioral of septSegments_Top is
+
+component septSegments_encodeur is
+Port(
+ i_AFF : in STD_LOGIC_VECTOR(3 downto 0); -- caractère à afficher
+ o_CharacterePourSim : out string(1 to 1); -- pour simulation seulement
+ o_Seg : out STD_LOGIC_VECTOR(6 downto 0) -- encodage 7-segments
+ );
+end component;
+
+component septSegments_refreshPmod is
+generic(const_CLK_MHz : integer := 100); -- horloge en MHz, typique 100 MHz
+Port(
+ clk : in STD_LOGIC; -- horloge systeme, typique 100 MHz (preciser par le constante)
+ i_SSD0 : in STD_LOGIC_VECTOR(6 downto 0); -- donnee a afficher sur 1er chiffre
+ i_SSD1 : in STD_LOGIC_VECTOR(6 downto 0); -- donnee a afficher sur 2e chiffre
+ JPmod : out STD_LOGIC_VECTOR(7 downto 0) -- sorties directement adaptees au connecteur PmodSSD
+);
+end component;
+
+
+signal s_segment_lsb : STD_LOGIC_VECTOR (6 downto 0);
+signal s_segment_msb : STD_LOGIC_VECTOR (6 downto 0);
+
+begin
+
+
+inst_segm_lsb : septSegments_encodeur
+Port map(
+ i_AFF => i_AFF0,
+ o_CharacterePourSim => o_AFFSSD_Sim(1 downto 1),
+ o_Seg => s_segment_lsb
+ );
+
+inst_segm_msb : septSegments_encodeur
+Port map(
+ i_AFF => i_AFF1,
+ o_CharacterePourSim => o_AFFSSD_Sim(2 downto 2),
+ o_Seg => s_segment_msb
+ );
+
+inst_refresh : septSegments_refreshPmod
+--generic(const_CLK_MHz : integer := 100); -- horloge en MHz, typique 100 MHz
+Port map(
+ clk => clk,
+ i_SSD0 => s_segment_lsb,
+ i_SSD1 => s_segment_msb,
+ JPmod => o_AFFSSD
+);
+
+end Behavioral;
+
diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_encodeur.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_encodeur.vhd new file mode 100644 index 0000000..5419a0c --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_encodeur.vhd @@ -0,0 +1,120 @@ +---------------------------------------------------------------------------------------------
+-- circuit affhex_pmodssd.vhd
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version : 2.0
+-- Nomenclature : 0.8 GRAMS
+-- Date : revision 23 octobre 2018
+-- Auteur(s) : Réjean Fontaine, Daniel Dalle
+-- Technologies : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+-- Outils : vivado 2016.1 64 bits, vivado 2018.2
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Affichage sur module de 2 chiffes (7 o_Segents) sur PmodSSD
+-- reference https://reference.digilentinc.com/reference/pmod/pmodssd/start
+-- PmodSSD™ Reference Manual Doc: 502-126 Digilent, Inc.
+--
+-- Revisions
+-- mise a jour D Dalle 22 octobre 2018 corrections, simplifications
+-- mise a jour D Dalle 15 octobre documentation affhex_pmodssd_sol_v0.vhd
+-- mise a jour D Dalle 12 septembre pour eviter l'usage d'une horloge interne
+-- mise a jour D Dalle 7 septembre, calcul des constantes.
+-- mise a jour D Dalle 5 septembre 2018, nom affhexPmodSSD, 6 septembre :division horloge
+-- module de commande le l'afficheur 2 o_Segents 2 digits sur pmod
+-- Daniel Dalle revision pour sortir les signaux du connecteur Pmod directement
+-- Daniel Dalle 30 juillet 2018:
+-- revision pour une seule entre sur 8 bits affichee sur les deux chiffres Hexa
+--
+-- Creation selon affhex7segx4v3.vhd
+-- (Daniel Dalle, Réjean Fontaine Universite de Sherbrooke, Departement GEGI)
+-- 26 septembre 2011, revision 12 juin 2012, 25 janvier 2013, 7 mai 2015
+-- Contrôle de l'afficheur a sept o_Segent (BASYS2 - NEXYS2)
+-- horloge 100MHz et diviseur interne
+---------------------------------------------------------------------------------------------
+-- À faire :
+--
+--
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity septSegments_encodeur is
+ Port(
+ i_AFF : in STD_LOGIC_VECTOR(3 downto 0); -- caractère à afficher
+ o_CharacterePourSim : out string(1 to 1); -- pour simulation seulement
+ o_Seg : out STD_LOGIC_VECTOR(6 downto 0) -- encodage 7-segments
+ );
+end septSegments_encodeur;
+
+architecture Behavioral of septSegments_encodeur is
+
+
+-- fonction réservée pour l'affichage en simulation seulement
+function segment2String(display : std_logic_vector( 6 downto 0))
+ return string is
+ variable v_ReturnString : string(1 to 1);
+ begin
+ case display is
+ when "0111111" => v_ReturnString := "0"; -- 0
+ when "0000110" => v_ReturnString := "1"; -- 1
+ when "1011011" => v_ReturnString := "2"; -- 2
+ when "1001111" => v_ReturnString := "3"; -- 3
+ when "1100110" => v_ReturnString := "4"; -- 4
+ when "1101101" => v_ReturnString := "5"; -- 5
+ when "1111101" => v_ReturnString := "6"; -- 6
+ when "0000111" => v_ReturnString := "7"; -- 7
+ when "1111111" => v_ReturnString := "8"; -- 8
+ when "1101111" => v_ReturnString := "9"; -- 9
+ when "1110111" => v_ReturnString := "A"; -- A
+ when "1111100" => v_ReturnString := "B"; -- b
+ when "0111001" => v_ReturnString := "C"; -- C
+ when "1011110" => v_ReturnString := "D"; -- d
+ when "1111001" => v_ReturnString := "E"; -- E
+ when "1110001" => v_ReturnString := "F"; -- F
+ when "1000000" => v_ReturnString := "-"; -- négatif
+ when "1010000" => v_ReturnString := "r"; -- r pour erreur
+ when others => v_ReturnString := "_"; -- code non reconnu
+ end case;
+ return v_ReturnString;
+ end segment2String;
+ -- fin de la fonction
+
+
+ signal s_Seg : STD_LOGIC_VECTOR(6 downto 0);
+
+begin
+
+-- correspondance des o_Segents des afficheurs
+o_Segent: process (i_AFF)
+ begin
+ case i_AFF is
+ -- "gfedcba"
+ when "0000" => s_Seg <= "0111111"; -- 0
+ when "0001" => s_Seg <= "0000110"; -- 1
+ when "0010" => s_Seg <= "1011011"; -- 2
+ when "0011" => s_Seg <= "1001111"; -- 3
+ when "0100" => s_Seg <= "1100110"; -- 4
+ when "0101" => s_Seg <= "1101101"; -- 5
+ when "0110" => s_Seg <= "1111101"; -- 6
+ when "0111" => s_Seg <= "0000111"; -- 7
+ when "1000" => s_Seg <= "1111111"; -- 8
+ when "1001" => s_Seg <= "1101111"; -- 9
+ when "1010" => s_Seg <= "1110111"; -- A
+ when "1011" => s_Seg <= "1111100"; -- B
+ when "1100" => s_Seg <= "0111001"; -- C
+ when "1101" => s_Seg <= "1011110"; -- D
+ when "1110" => s_Seg <= "1111001"; -- E
+ when "1111" => s_Seg <= "1110001"; -- F
+ when others => s_Seg <= "0000000";
+ end case;
+ end process;
+
+
+ o_CharacterePourSim <= segment2String(s_Seg);
+ o_Seg <= s_Seg ;
+
+end Behavioral;
+
diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_refreshPmod.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_refreshPmod.vhd new file mode 100644 index 0000000..0e92407 --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_refreshPmod.vhd @@ -0,0 +1,66 @@ +---------------------------------------------------------------------------------------------
+-- circuit affhex_pmodssd.vhd
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- APP de circuits logiques
+-- Auteur(s) : Réjean Fontaine, Daniel Dalle, Marc-André Tétrault
+-- Technologies : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Séparation du décodage 7-segments pour faciliter un affichage en simulation
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity septSegments_refreshPmod is
+ generic(const_CLK_MHz : integer := 100); -- horloge en MHz, typique 100 MHz
+ Port(
+ clk : in STD_LOGIC; -- horloge systeme, typique 100 MHz (preciser par le constante)
+ i_SSD0 : in STD_LOGIC_VECTOR(6 downto 0); -- donnee a afficher sur 1er chiffre
+ i_SSD1 : in STD_LOGIC_VECTOR(6 downto 0); -- donnee a afficher sur 2e chiffre
+ JPmod : out STD_LOGIC_VECTOR(7 downto 0) -- sorties directement adaptees au connecteur PmodSSD
+ );
+end septSegments_refreshPmod;
+
+architecture Behavioral of septSegments_refreshPmod is
+
+ -- realisation compteur division horloge pour multiplexer affichage SSD
+ -- constante pour ajuster selon l horloge pilote du controle des afficheurs
+ constant CLK_SSD_KHz_des : integer := 5; --Khz -- horloge desiree pour raffraichir afficheurs 7 segment
+ constant const_div_clk_SSD : integer := (const_CLK_MHz * 1000 / CLK_SSD_KHz_des - 1);
+ constant cdvia : std_logic_vector(15 downto 0) := conv_std_logic_vector(const_div_clk_SSD, 16); -- donne 5 KHz soit 200 us
+
+ signal counta : std_logic_vector(15 downto 0) := (others => '0');
+ signal segm : std_logic_vector(6 downto 0);
+ signal SEL : std_logic := '0';
+
+begin
+
+ -- selection chiffre pour affichage
+ local_CLK_proc : process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ counta <= counta + 1;
+ if (counta = cdvia) then -- devrait se produire aux 200 us approx
+ counta <= (others => '0');
+ SEL <= not SEL; -- bascule de la selection du chiffre (0 ou 1)
+ -- SEL devrait avoir periode de 400 us approx
+
+ -- l'ordre n'est pas important pour l'affichage physique
+ if (SEL = '1') then
+ segm(6 downto 0) <= i_SSD0;
+ else
+ segm(6 downto 0) <= i_SSD1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ JPmod <= SEL & segm;
+
+end Behavioral;
+
diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/synchro_module_v2.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/synchro_module_v2.vhd new file mode 100644 index 0000000..93494e6 --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/imports/src/synchro_module_v2.vhd @@ -0,0 +1,130 @@ +---------------------------------------------------------------------------------------------
+-- synchro_module_v2.vhd
+---------------------------------------------------------------------------------------------
+-- Generation d'horloge et de signaux de synchronisation
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+--
+-- Version : 2.0
+-- Nomenclature : ref GRAMS
+-- Date : 13 sept. 2018, 4 decembre 2018
+-- Auteur(s) : Daniel Dalle
+-- Technologies : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+-- Outils : vivado 2018.2 64 bits
+--
+--------------------------------
+-- Description
+--------------------------------
+-- Génération de signaux de synchronisation, incluant des "strobes"
+-- Voir les comentaires dans la declaration entity pour le description des signaux
+-- revisions
+-- 4 decembre 2018 : reduction des signaux de sorties
+-- 16 octobre 2018 : documentation
+-- 13 septembre 2018: creation
+--
+--------------------------------
+-- À FAIRE:
+--------------------------------
+--
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.all; -- requis pour les constantes etc.
+use IEEE.STD_LOGIC_UNSIGNED.ALL; -- pour les additions dans les compteurs
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity synchro_module_v2 is
+generic (const_CLK_syst_MHz: integer := 100);
+ Port (
+ clkm : in STD_LOGIC; -- Entrée horloge maitre
+ o_clk_5MHz : out STD_LOGIC; -- horloge divisee via bufg
+ o_S_1Hz : out STD_LOGIC -- Signal temoin 1 Hz (0,99952 Hz)
+ );
+end synchro_module_v2;
+
+architecture Behavioral of synchro_module_v2 is
+
+-- component strb_gen is
+-- Port (
+-- CLK : in STD_LOGIC; -- Entrée horloge maitre
+-- i_don : in STD_LOGIC; -- signal pour generer strobe au front montant
+-- o_stb : out STD_LOGIC -- strobe synchrone resultant
+-- );
+-- end component;
+
+ -- constantes pour les diviseurs
+ constant CLKp_MHz_des : integer := 5; -- Mhz
+ constant constante_diviseur_p: integer :=(const_CLK_syst_MHz/(2*CLKp_MHz_des)); -- considerant toggle sur le signal Clkp5MHzint
+ --constant constante_diviseur_p: integer :=(const_CLK_syst_MHz/(CLKp_MHz_des)-1);
+ constant cdiv1 : std_logic_vector(3 downto 0):= conv_std_logic_vector(constante_diviseur_p, 4);
+ constant cdiv2 : std_logic_vector(4 downto 0) := conv_std_logic_vector (25, 5) ; -- overflow a Clkp5MHzint/26 = 192.3 kHz soit 5.2 us
+ constant cdiv3 : std_logic_vector(15 downto 0):= conv_std_logic_vector (1848, 16); -- overflow a Clk200kHzInt / 1924 = 99.952 = ~100 Hz soit 10.005 ms (t réel)
+ constant cdiv4 : std_logic_vector(7 downto 0) := conv_std_logic_vector (99, 8) ; -- o_S1Hz = o_clk3 / 100 = 1 Hz soit 1 s
+
+ --
+ signal ValueCounter5MHz : std_logic_vector(4 downto 0) := "00000";
+ signal ValueCounter200kHz : std_logic_vector(4 downto 0) := "00000";
+ signal ValueCounter100Hz : std_logic_vector(15 downto 0) := "0000000000000000";
+ signal ValueCounter1Hz : std_logic_vector(7 downto 0) := "00000000";
+
+ signal d_s5MHzInt : std_logic := '0';
+ signal clk_5MHzInt : std_logic := '0';
+ signal d_s1HzInt : std_logic := '0' ;
+ signal d_s100HzInt : std_logic := '0' ;
+ signal d_strobe_100HzInt : std_logic := '0' ;
+
+
+begin
+
+-- buffer d'horloge nécessaire pour implémentation d'un signal d'horloge
+-- a distribuer dans tout le circuit
+ClockBuffer: bufg
+port map(
+ I => d_s5MHzInt,
+ O => clk_5MHzInt
+ );
+
+--inst_strb_100Hz : strb_gen
+-- Port map (
+-- CLK => clk_5MHzInt,
+-- i_don => d_s100HzInt,
+-- o_stb => d_strobe_100HzInt
+-- );
+
+o_clk_5MHz <= clk_5MHzInt;
+--o_S_100Hz <= d_s100HzInt;
+o_S_1Hz <= d_s1HzInt;
+--o_stb_100Hz <= d_strobe_100HzInt;
+
+process(clkm)
+begin
+ if(clkm'event and clkm = '1') then
+ ValueCounter5MHz <= ValueCounter5MHz + 1;
+ if (ValueCounter5MHz = cdiv1) then -- evenement se produit aux 100 approx ns
+ ValueCounter5MHz <= "00000";
+ d_s5MHzInt <= Not d_s5MHzInt; -- pour generer horloge a exterieur du module (prevoir bufg)
+ ValueCounter200kHz <= ValueCounter200kHz + 1;
+ if (ValueCounter200kHz = cdiv2) then -- evenement se produit aux 5 us approx
+ ValueCounter200kHz <= "00000";
+ ValueCounter100Hz <= ValueCounter100Hz + 1;
+ if (ValueCounter100Hz = cdiv3) then -- evenement se produit aux 5 ms approx
+ ValueCounter100Hz <= "0000000000000000";
+ -- d_s100HzInt <= Not d_s100HzInt;
+ ValueCounter1Hz <= ValueCounter1Hz + 1;
+ if (ValueCounter1Hz = cdiv4) then -- evenement se produit aux 500 ms approx
+ ValueCounter1Hz <= "00000000";
+ d_s1HzInt <= Not d_s1HzInt;
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd new file mode 100644 index 0000000..0b1ed7c --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd @@ -0,0 +1,49 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/30/2025 03:19:19 PM +-- Design Name: +-- Module Name: Add1BitA - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Add1BitA is + Port ( X : in STD_LOGIC; + Y : in STD_LOGIC; + Ci : in STD_LOGIC; + O : out STD_LOGIC; + Co : out STD_LOGIC); +end Add1BitA; + +architecture Behavioral of Add1BitA is + +begin + + O <= (X xor Y) xor Ci; + Co <= ((X xor Y) and Ci) or (X and Y); + +end; diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd new file mode 100644 index 0000000..b00716e --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd @@ -0,0 +1,47 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/30/2025 03:19:19 PM +-- Design Name: +-- Module Name: Add1BitB - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Add1BitB is + Port ( X : in STD_LOGIC; + Y : in STD_LOGIC; + Ci : in STD_LOGIC; + O : out STD_LOGIC; + Co : out STD_LOGIC); +end Add1BitB; + +architecture Behavioral of Add1BitB is + +begin + + +end Behavioral; diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd new file mode 100644 index 0000000..be2cf13 --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd @@ -0,0 +1,47 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/30/2025 03:19:19 PM +-- Design Name: +-- Module Name: Add4Bits - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Add4Bits is + Port ( X : in STD_LOGIC_VECTOR (0 to 3); + Y : in STD_LOGIC_VECTOR (0 to 3); + Ci : in STD_LOGIC; + O : out STD_LOGIC_VECTOR (0 to 3); + Co : out STD_LOGIC); +end Add4Bits; + +architecture Behavioral of Add4Bits is + +begin + + +end Behavioral; diff --git a/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd b/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd new file mode 100644 index 0000000..7f5148d --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd @@ -0,0 +1,54 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/30/2025 01:11:03 PM +-- Design Name: +-- Module Name: full_adder - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity full_adder is + Port ( c_in : in STD_LOGIC; + a : in STD_LOGIC; + b : in STD_LOGIC; + o : out STD_LOGIC; + c_o : out STD_LOGIC); +end full_adder; + +architecture Behavioral of full_adder is + + signal aXb : STD_LOGIC; + +begin + + aXb <= a xor b; + + o <= aXb xor c_in; + c_o <= (aXb and c_in) or (a and b); + + +end Behavioral; diff --git a/pb_APP_log_comb.xpr b/pb_APP_log_comb.xpr new file mode 100644 index 0000000..fe9d7e0 --- /dev/null +++ b/pb_APP_log_comb.xpr @@ -0,0 +1,283 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> + +<Project Version="7" Minor="54" Path="/home/master/Dropbox/A/scholar/sherbrooke/25-05-S4/app1/problematique/pb_APP_log_comb.xpr"> + <DefaultLaunch Dir="$PRUNDIR"/> + <Configuration> + <Option Name="Id" Val="fbfa33bf844143359da4f5e7109fc83c"/> + <Option Name="Part" Val="xc7z010clg400-1"/> + <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> + <Option Name="CompiledLibDirXSim" Val=""/> + <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> + <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> + <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/> + <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> + <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> + <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> + <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> + <Option Name="SimulatorInstallDirModelSim" Val=""/> + <Option Name="SimulatorInstallDirQuesta" Val=""/> + <Option Name="SimulatorInstallDirIES" Val=""/> + <Option Name="SimulatorInstallDirXcelium" Val=""/> + <Option Name="SimulatorInstallDirVCS" Val=""/> + <Option Name="SimulatorInstallDirRiviera" Val=""/> + <Option Name="SimulatorInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorGccInstallDirModelSim" Val=""/> + <Option Name="SimulatorGccInstallDirQuesta" Val=""/> + <Option Name="SimulatorGccInstallDirIES" Val=""/> + <Option Name="SimulatorGccInstallDirXcelium" Val=""/> + <Option Name="SimulatorGccInstallDirVCS" Val=""/> + <Option Name="SimulatorGccInstallDirRiviera" Val=""/> + <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> + <Option Name="TargetLanguage" Val="VHDL"/> + <Option Name="SimulatorLanguage" Val="VHDL"/> + <Option Name="BoardPart" Val="digilentinc.com:zybo-z7-10:part0:1.0"/> + <Option Name="SourceMgmtMode" Val="DisplayOnly"/> + <Option Name="ActiveSimSet" Val="sim_1"/> + <Option Name="DefaultLib" Val="xil_defaultlib"/> + <Option Name="ProjectType" Val="Default"/> + <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> + <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/> + <Option Name="IPCachePermission" Val="read"/> + <Option Name="IPCachePermission" Val="write"/> + <Option Name="EnableCoreContainer" Val="FALSE"/> + <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> + <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> + <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> + <Option Name="EnableBDX" Val="FALSE"/> + <Option Name="DSABoardId" Val="zybo-z7-10"/> + <Option Name="DSADescription" Val="Vivado generated DSA"/> + <Option Name="DSAEmuDir" Val="emu"/> + <Option Name="WTXSimLaunchSim" Val="184"/> + <Option Name="WTModelSimLaunchSim" Val="0"/> + <Option Name="WTQuestaLaunchSim" Val="0"/> + <Option Name="WTIesLaunchSim" Val="0"/> + <Option Name="WTVcsLaunchSim" Val="0"/> + <Option Name="WTRivieraLaunchSim" Val="0"/> + <Option Name="WTActivehdlLaunchSim" Val="0"/> + <Option Name="WTXSimExportSim" Val="0"/> + <Option Name="WTModelSimExportSim" Val="0"/> + <Option Name="WTQuestaExportSim" Val="0"/> + <Option Name="WTIesExportSim" Val="0"/> + <Option Name="WTVcsExportSim" Val="0"/> + <Option Name="WTRivieraExportSim" Val="0"/> + <Option Name="WTActivehdlExportSim" Val="0"/> + <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> + <Option Name="XSimRadix" Val="hex"/> + <Option Name="XSimTimeUnit" Val="ns"/> + <Option Name="XSimArrayDisplayLimit" Val="1024"/> + <Option Name="XSimTraceLimit" Val="65536"/> + <Option Name="SimTypes" Val="rtl"/> + <Option Name="SimTypes" Val="bfm"/> + <Option Name="SimTypes" Val="tlm"/> + <Option Name="SimTypes" Val="tlm_dpi"/> + <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> + <Option Name="DcpsUptoDate" Val="TRUE"/> + </Configuration> + <FileSets Version="1" Minor="31"> + <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/imports/src/septSegments_encodeur.vhd"> + <FileInfo SFType="VHDL2008"> + <Attr Name="ImportPath" Val="$PPRDIR/../src/septSegments_encodeur.vhd"/> + <Attr Name="ImportTime" Val="1635539909"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/imports/src/septSegments_refreshPmod.vhd"> + <FileInfo SFType="VHDL2008"> + <Attr Name="ImportPath" Val="$PPRDIR/../src/septSegments_refreshPmod.vhd"/> + <Attr Name="ImportTime" Val="1651164618"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/imports/src/septSegments_Top.vhd"> + <FileInfo SFType="VHDL2008"> + <Attr Name="ImportPath" Val="$PPRDIR/../src/septSegments_Top.vhd"/> + <Attr Name="ImportTime" Val="1651164797"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/imports/src/synchro_module_v2.vhd"> + <FileInfo SFType="VHDL2008"> + <Attr Name="ImportPath" Val="$PPRDIR/../src/synchro_module_v2.vhd"/> + <Attr Name="ImportTime" Val="1635539909"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/imports/src/AppCombi_top.vhd"> + <FileInfo SFType="VHDL2008"> + <Attr Name="ImportPath" Val="$PPRDIR/../src/AppCombi_top.vhd"/> + <Attr Name="ImportTime" Val="1651163486"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/new/full_adder.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/new/Add1BitA.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/new/Add1BitB.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/new/Add4Bits.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="full_adder"/> + </Config> + </FileSet> + <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> + <Filter Type="Constrs"/> + <File Path="$PSRCDIR/constrs_1/imports/contraintes/AppCombi_top.xdc"> + <FileInfo> + <Attr Name="ImportPath" Val="$PPRDIR/../contraintes/AppCombi_top.xdc"/> + <Attr Name="ImportTime" Val="1641412072"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + </FileInfo> + </File> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sim_1/imports/verif/AppCombi_top_tb.vhd"> + <FileInfo SFType="VHDL2008"> + <Attr Name="ImportPath" Val="$PPRDIR/../verif/AppCombi_top_tb.vhd"/> + <Attr Name="ImportTime" Val="1640205813"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="AppCombi_top_tb"/> + <Option Name="TopLib" Val="xil_defaultlib"/> + <Option Name="TransportPathDelay" Val="0"/> + <Option Name="TransportIntDelay" Val="0"/> + <Option Name="SelectedSimModel" Val="rtl"/> + <Option Name="PamDesignTestbench" Val=""/> + <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/> + <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> + <Option Name="PamPseudoTop" Val="pseudo_tb"/> + <Option Name="SrcSet" Val="sources_1"/> + <Option Name="Incremental" Val="0"/> + </Config> + </FileSet> + <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> + <Filter Type="Utils"/> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + </FileSets> + <Simulators> + <Simulator Name="XSim"> + <Option Name="Description" Val="Vivado Simulator"/> + <Option Name="CompiledLib" Val="0"/> + </Simulator> + <Simulator Name="ModelSim"> + <Option Name="Description" Val="ModelSim Simulator"/> + </Simulator> + <Simulator Name="Questa"> + <Option Name="Description" Val="Questa Advanced Simulator"/> + </Simulator> + <Simulator Name="IES"> + <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/> + </Simulator> + <Simulator Name="Xcelium"> + <Option Name="Description" Val="Xcelium Parallel Simulator"/> + </Simulator> + <Simulator Name="VCS"> + <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> + </Simulator> + <Simulator Name="Riviera"> + <Option Name="Description" Val="Riviera-PRO Simulator"/> + </Simulator> + </Simulators> + <Runs Version="1" Minor="15"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/tetm2701/Documents/Repos/git_gen420430A-circuits-combinatoires/Ressources/Vivado/pb_APP_log_comb/pb_APP_log_comb.srcs/utils_1/imports/synth_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/> + <Step Id="synth_design"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/tetm2701/Documents/Repos/git_gen420430A-circuits-combinatoires/Ressources/Vivado/pb_APP_log_comb/pb_APP_log_comb.srcs/utils_1/imports/impl_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + </Runs> + <Board> + <Jumpers/> + </Board> + <DashboardSummary Version="1" Minor="0"> + <Dashboards> + <Dashboard Name="default_dashboard"> + <Gadgets> + <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/> + </Gadget> + <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/> + </Gadget> + <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/> + </Gadget> + <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/> + </Gadget> + <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/> + <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/> + <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/> + </Gadget> + <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/> + </Gadget> + </Gadgets> + </Dashboard> + <CurrentDashboard>default_dashboard</CurrentDashboard> + </Dashboards> + </DashboardSummary> +</Project> |