Parity testbench

2 files changed, 146 insertions, 5 deletions

diff --git a/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd
index 79fffad..39a5819 100644
--- a/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd
+++ b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd
@@ -34,8 +34,8 @@ use IEEE.STD_LOGIC_1164.ALL;
 --use UNISIM.VComponents.all;

 

 -- requis pour enoncés de type mem_valeurs_tests(to_integer( unsigned(table_valeurs_adr(9 downto 6) )));

-use ieee.numeric_std.ALL;          --

-use IEEE.STD_LOGIC_UNSIGNED.ALL;   --

+use ieee.numeric_std.ALL;

+use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

 

 entity AppCombi_top_tb is

@@ -202,9 +202,9 @@ begin
            resultat_attendu <= vecteur_test_sim(13 downto 9);

 

            -- Assignation of variables to add4bit

-           add_a_sim     <= vecteur_test_sim(8 downto 5);

-           add_b_sim     <= vecteur_test_sim(4 downto 1);

-           add_cin_sim   <= vecteur_test_sim(0);

+           add_a_sim   <= vecteur_test_sim(8 downto 5);

+           add_b_sim   <= vecteur_test_sim(4 downto 1);

+           add_cin_sim <= vecteur_test_sim(0);

 

            wait for delai_sim;

 

diff --git a/pb_APP_log_comb.srcs/sources_1/new/parity_check_tb.vhd b/pb_APP_log_comb.srcs/sources_1/new/parity_check_tb.vhd
new file mode 100644
index 0000000..c3af954
--- /dev/null
+++ b/pb_APP_log_comb.srcs/sources_1/new/parity_check_tb.vhd
@@ -0,0 +1,141 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 05/03/2025 07:14:35 PM
+-- Design Name:
+-- Module Name: Decodeur_3_8_tb - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Parity_check_tb is
+end Parity_check_tb;
+
+architecture Behavioral of Parity_check_tb is
+
+  component parity_check port (
+    ADCbin : in  STD_LOGIC_VECTOR (3 downto 0);
+    S1     : in  STD_LOGIC;
+    Parite : out STD_LOGIC);
+  end component;
+
+  signal input_bits_sim : STD_LOGIC_VECTOR (2 downto 0);
+  signal input_cfg_sim  : STD_LOGIC;
+  signal bus_out_sim    : STD_LOGIC;
+  signal expected       : STD_LOGIC;
+
+  ----------------------------------------------------------------------------
+  -- Test bench usage signals
+  ----------------------------------------------------------------------------
+  constant sysclk_Period    : time := 8 ns;
+  signal   clk_sim          : STD_LOGIC := '0';
+  signal   vecteur_test_sim : STD_LOGIC_VECTOR(10 downto 0);
+
+  ----------------------------------------------------------------------------
+  -- declaration d'un tableau pour soumettre un vecteur de test
+  ----------------------------------------------------------------------------
+  constant parity_test_count: integer := 8;
+  type parity_test_table is array (integer range 0 to parity_test_count) of std_logic_vector(4 downto 0);
+      constant mem_test_values : parity_test_table := (
+        -- IN defines the input data
+        -- RHS is the bit that must be "appended" to make the 1-sum even/uneven
+
+        -- IN   even  uneven
+        "000" & "0" & "1",
+        "001" & "1" & "0",
+        "010" & "1" & "0",
+        "011" & "0" & "1",
+        "100" & "1" & "0",
+        "101" & "0" & "1",
+        "110" & "0" & "1",
+        "111" & "0" & "0",
+
+        -- DO NOT DELETE
+        others => "000" & "0" & "1"
+      );
+
+begin
+
+  parity_checker: parity_check port map (
+    ADCbin => input_bits_sim,
+    S1     => input_cfg_sim,
+    Parite => expected);
+
+  -- Section banc de test
+  ----------------------------------------
+	-- generation horloge
+	----------------------------------------
+  process
+  begin
+      clk_sim <= '1';  -- init
+      loop
+          wait for sysclk_Period/2;
+          clk_sim <= not clk_sim;    -- invert clock value
+      end loop;
+  end process;
+  ----------------------------------------
+  ----------------------------------------
+  -- test bench
+  tb : process
+    variable delai_sim : time  := 50 ns;
+    variable table_valeurs_adr : integer range 0 to parity_test_count;
+
+  -------------------------------------------------
+  -- TEST EVEN PARITY (button pressed -> S1 = '1')
+  -------------------------------------------------
+  begin
+    table_valeurs_adr := 0;
+    for index in 0 to   mem_test_values'length-1 loop
+      vecteur_test_sim <= mem_test_values(table_valeurs_adr);
+
+      ----------------------------------------
+      -- Assignation des signals de tests aux valeurs fetched de la table.
+      ----------------------------------------
+	    input_bits_sim <= vecteur_test_sim(2 downto 0);
+      input_cfg_sim <= '1'; -- PRESSED BUTTON: TEST EVEN PARITY
+	    expected <= vecteur_test_sim(3);
+	    ----------------------------------------
+      wait for delai_sim;
+
+        -- Compare results. Des impression dans le terminal sont fait uniquement lors d'erreurs.
+        assert (expected = bus_out_sim)
+          report "Parity_check: Incorrect parity resolution = " &
+            STD_LOGIC'image(bus_out_sim) &
+            ", Expected = " &
+            STD_LOGIC'image(expected)
+            severity warning;
+
+
+            if(table_valeurs_adr = parity_test_count) then
+                exit;
+            end if;
+            table_valeurs_adr := table_valeurs_adr + 1;
+    end loop;
+    wait;
+  end process;
+end Behavioral;