Annex work

5 files changed, 201 insertions, 58 deletions

diff --git a/rapport/annexe.tex b/rapport/annexe.tex
index f15f688..0c43f81 100644
--- a/rapport/annexe.tex
+++ b/rapport/annexe.tex
@@ -1,6 +1,7 @@
 \newpage
 \appendix
 \section{Code VHDL}
+\todo{Finish this this}
 
 \begin{figure}[H]
   \tiny
@@ -11,8 +12,40 @@
 \caption{Module Thermo2bin}
 \end{figure}
 
-\section{Simulations}
+\begin{figure}[H]
+  \tiny
+\centering
+\begin{varwidth}{\linewidth}
+  \input{assets/code/add4bits.tex}
+\end{varwidth}
+\caption{Module Add4Bits}
+\end{figure}
 
-\section{Tables de Vérité et Karnaugh}
+\begin{figure}[H]
+  \tiny
+\centering
+\begin{varwidth}{\linewidth}
+  \input{assets/code/add1bita.tex}
+\end{varwidth}
+\caption{Module Add1BitA}
+\end{figure}
+
+\begin{figure}[H]
+  \tiny
+\centering
+\begin{varwidth}{\linewidth}
+  \input{assets/code/add1bitb.tex}
+\end{varwidth}
+\caption{Module Add1BitB}
+\end{figure}
+
+\section{Schémas}
 
+\todo{Schéma bloc}\\
+\todo{Simulations}
+
+
+\section{Tables de Vérité et Karnaugh}
 
+\todo{Verite}\\
+\todo{Karnaugh}
diff --git a/rapport/assets/code/add1bita.tex b/rapport/assets/code/add1bita.tex
new file mode 100644
index 0000000..238a6b2
--- /dev/null
+++ b/rapport/assets/code/add1bita.tex
@@ -0,0 +1,10 @@
+\begin{verbatim}
+architecture Behavioral of Add1BitA is
+
+begin
+
+  O  <= (X xor Y) xor Ci;
+  Co <= ((X xor Y) and Ci) or (X and Y);
+
+end;
+\end{verbatim}
diff --git a/rapport/assets/code/add1bitb.tex b/rapport/assets/code/add1bitb.tex
new file mode 100644
index 0000000..c4c48d7
--- /dev/null
+++ b/rapport/assets/code/add1bitb.tex
@@ -0,0 +1,45 @@
+\begin{verbatim}
+architecture Behavioral of Add1BitB is
+
+begin
+
+Adder: process(X, Y, Ci) is variable buf: STD_LOGIC_VECTOR(2 downto 0);
+begin
+  buf(0) := X;
+  buf(1) := Y;
+  buf(2) := Ci;
+
+  case (buf) is
+    when "000" =>
+      O  <= '0';
+      Co <= '0';
+    when "001" =>
+      O  <= '1';
+      Co <= '0';
+    when "010" =>
+      O  <= '1';
+      Co <= '0';
+    when "011" =>
+      O  <= '0';
+      Co <= '1';
+    when "100" =>
+      O  <= '1';
+      Co <= '0';
+    when "101" =>
+      O  <= '0';
+      Co <= '1';
+    when "110" =>
+      O  <= '0';
+      Co <= '1';
+    when "111" =>
+      O  <= '1';
+      Co <= '1';
+    when others =>
+      O  <= '0';
+      Co <= '0';
+  end case;
+
+end process Adder;
+
+end Behavioral;
+\end{verbatim}
diff --git a/rapport/assets/code/add4bits.tex b/rapport/assets/code/add4bits.tex
new file mode 100644
index 0000000..3342e48
--- /dev/null
+++ b/rapport/assets/code/add4bits.tex
@@ -0,0 +1,55 @@
+\begin{verbatim}
+architecture Behavioral of Add4Bits is
+
+  signal bufA : STD_LOGIC;
+  signal bufB : STD_LOGIC;
+  signal bufC : STD_LOGIC;
+
+  component Add1BitA is Port (
+    X : in STD_LOGIC;
+    Y : in STD_LOGIC;
+    Ci: in STD_LOGIC;
+    O : out STD_LOGIC;
+    Co: out STD_LOGIC);
+  end component;
+
+  component Add1BitB is Port (
+    X : in STD_LOGIC;
+    Y : in STD_LOGIC;
+    Ci: in STD_LOGIC;
+    O : out STD_LOGIC;
+    Co: out STD_LOGIC);
+  end component;
+
+begin
+
+  first : Add1BitB port map (
+    X  => A(0),
+    Y  => B(0),
+    Ci => C,
+    O => R(0),
+    Co => bufA);
+
+  sec : Add1BitB port map (
+    X  => A(1),
+    Y  => B(1),
+    Ci => bufA,
+    O => R(1),
+    Co => bufB);
+
+  third : Add1BitA port map (
+    X  => A(2),
+    Y  => B(2),
+    Ci => bufB,
+    O => R(2),
+    Co => bufC);
+
+  fourth : Add1BitA port map (
+    X  => A(3),
+    Y  => B(3),
+    Ci => bufC,
+    O => R(3),
+    Co => Rc);
+
+end Behavioral;
+\end{verbatim}
diff --git a/rapport/assets/code/thermo2bin.tex b/rapport/assets/code/thermo2bin.tex
index b4e60a4..c8d83d2 100644
--- a/rapport/assets/code/thermo2bin.tex
+++ b/rapport/assets/code/thermo2bin.tex
@@ -1,63 +1,63 @@
 \begin{verbatim}
 architecture Behavioral of Thermo2Bin is
-    signal first_segment_of_four : STD_LOGIC_VECTOR(3 downto 0);
-    signal second_segment_of_four : STD_LOGIC_VECTOR(3 downto 0);
-    signal third_segment_of_four : STD_LOGIC_VECTOR(3 downto 0);
-
-    component Add4Bits is
-        Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
-            B : in STD_LOGIC_VECTOR (3 downto 0);
-            C : in STD_LOGIC;
-            R : out STD_LOGIC_VECTOR (3 downto 0);
-            Rc : out STD_LOGIC);
-    end component;
-
-    signal first_plus_second : STD_LOGIC_VECTOR(3 downto 0);
-    signal carry_out_first_plus_second : STD_LOGIC;
-    signal last_carry_out : STD_LOGIC;
+  signal first_segment_of_four : STD_LOGIC_VECTOR(3 downto 0);
+  signal second_segment_of_four : STD_LOGIC_VECTOR(3 downto 0);
+  signal third_segment_of_four : STD_LOGIC_VECTOR(3 downto 0);
+
+  component Add4Bits is
+    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
+      B : in STD_LOGIC_VECTOR (3 downto 0);
+      C : in STD_LOGIC;
+      R : out STD_LOGIC_VECTOR (3 downto 0);
+      Rc : out STD_LOGIC);
+  end component;
+
+  signal first_plus_second : STD_LOGIC_VECTOR(3 downto 0);
+  signal carry_out_first_plus_second : STD_LOGIC;
+  signal last_carry_out : STD_LOGIC;
 
 begin
-    first_segment_of_four(3) <= '0';
-    first_segment_of_four(2) <= thermo_bus(11);
-    first_segment_of_four(1) <= NOT thermo_bus(11) AND thermo_bus(9);
-    first_segment_of_four(0) <= NOT thermo_bus(11) AND ((NOT thermo_bus(9) AND thermo_bus(8)) OR (thermo_bus(10) AND thermo_bus(9)));
-
-    second_segment_of_four(3) <= '0';
-    second_segment_of_four(2) <= thermo_bus(7);
-    second_segment_of_four(1) <= NOT thermo_bus(7) AND thermo_bus(5);
-    second_segment_of_four(0) <= NOT thermo_bus(7) AND ((NOT thermo_bus(5) AND thermo_bus(4)) OR (thermo_bus(6) AND thermo_bus(5)));
-
-    third_segment_of_four(3) <= '0';
-    third_segment_of_four(2) <= thermo_bus(3);
-    third_segment_of_four(1) <= NOT thermo_bus(3) AND thermo_bus(1);
-    third_segment_of_four(0) <= NOT thermo_bus(3) AND ((NOT thermo_bus(1) AND thermo_bus(0)) OR (thermo_bus(2) AND thermo_bus(1)));
-
-    first_plus_second_adder : Add4Bits port map (
-      A => first_segment_of_four,
-      B => second_segment_of_four,
-      R => first_plus_second,
-      Rc => carry_out_first_plus_second,
-      C => '0');
-
-    plus_third_adder : Add4Bits port map (
-      A => first_plus_second,
-      B => third_segment_of_four,
-      R => binary_out,
-      Rc => last_carry_out,
-      C => carry_out_first_plus_second);
-
-    error <= (
-    (thermo_bus(11) AND NOT thermo_bus(10)) OR
-    (thermo_bus(10) AND NOT thermo_bus(9)) OR
-    (thermo_bus(9)  AND NOT thermo_bus(8)) OR
-    (thermo_bus(8)  AND NOT thermo_bus(7)) OR
-    (thermo_bus(7)  AND NOT thermo_bus(6)) OR
-    (thermo_bus(6)  AND NOT thermo_bus(5)) OR
-    (thermo_bus(5)  AND NOT thermo_bus(4)) OR
-    (thermo_bus(4)  AND NOT thermo_bus(3)) OR
-    (thermo_bus(3)  AND NOT thermo_bus(2)) OR
-    (thermo_bus(2)  AND NOT thermo_bus(1)) OR
-    (thermo_bus(1)  AND NOT thermo_bus(0)));
+  first_segment_of_four(3) <= '0';
+  first_segment_of_four(2) <= thermo_bus(11);
+  first_segment_of_four(1) <= NOT thermo_bus(11) AND thermo_bus(9);
+  first_segment_of_four(0) <= NOT thermo_bus(11) AND ((NOT thermo_bus(9) AND thermo_bus(8)) OR (thermo_bus(10) AND thermo_bus(9)));
+
+  second_segment_of_four(3) <= '0';
+  second_segment_of_four(2) <= thermo_bus(7);
+  second_segment_of_four(1) <= NOT thermo_bus(7) AND thermo_bus(5);
+  second_segment_of_four(0) <= NOT thermo_bus(7) AND ((NOT thermo_bus(5) AND thermo_bus(4)) OR (thermo_bus(6) AND thermo_bus(5)));
+
+  third_segment_of_four(3) <= '0';
+  third_segment_of_four(2) <= thermo_bus(3);
+  third_segment_of_four(1) <= NOT thermo_bus(3) AND thermo_bus(1);
+  third_segment_of_four(0) <= NOT thermo_bus(3) AND ((NOT thermo_bus(1) AND thermo_bus(0)) OR (thermo_bus(2) AND thermo_bus(1)));
+
+  first_plus_second_adder : Add4Bits port map (
+    A => first_segment_of_four,
+    B => second_segment_of_four,
+    R => first_plus_second,
+    Rc => carry_out_first_plus_second,
+    C => '0');
+
+  plus_third_adder : Add4Bits port map (
+    A => first_plus_second,
+    B => third_segment_of_four,
+    R => binary_out,
+    Rc => last_carry_out,
+    C => carry_out_first_plus_second);
+
+  error <= (
+  (thermo_bus(11) AND NOT thermo_bus(10)) OR
+  (thermo_bus(10) AND NOT thermo_bus(9)) OR
+  (thermo_bus(9)  AND NOT thermo_bus(8)) OR
+  (thermo_bus(8)  AND NOT thermo_bus(7)) OR
+  (thermo_bus(7)  AND NOT thermo_bus(6)) OR
+  (thermo_bus(6)  AND NOT thermo_bus(5)) OR
+  (thermo_bus(5)  AND NOT thermo_bus(4)) OR
+  (thermo_bus(4)  AND NOT thermo_bus(3)) OR
+  (thermo_bus(3)  AND NOT thermo_bus(2)) OR
+  (thermo_bus(2)  AND NOT thermo_bus(1)) OR
+  (thermo_bus(1)  AND NOT thermo_bus(0)));
 
 end Behavioral;
 \end{verbatim}