More linting and working vhdl_ls config

3 files changed, 43 insertions, 43 deletions

diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd
index 0b1ed7c..ca031bb 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd
@@ -1,4 +1,4 @@
-----------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 -- Company:
 -- Engineer:
 --
@@ -16,7 +16,7 @@
 -- Revision 0.01 - File Created
 -- Additional Comments:
 --
-----------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 
 
 library IEEE;
@@ -31,19 +31,19 @@ use IEEE.STD_LOGIC_1164.ALL;
 --library UNISIM;
 --use UNISIM.VComponents.all;
 
-entity Add1BitA is
-    Port ( X : in STD_LOGIC;
-           Y : in STD_LOGIC;
-           Ci : in STD_LOGIC;
-           O : out STD_LOGIC;
-           Co : out STD_LOGIC);
+entity Add1BitA is Port (
+  X  : in  STD_LOGIC;
+  Y  : in  STD_LOGIC;
+  Ci : in  STD_LOGIC;
+  O  : out STD_LOGIC;
+  Co : out STD_LOGIC);
 end Add1BitA;
 
 architecture Behavioral of Add1BitA is
 
 begin
 
-  O <= (X xor Y) xor Ci;
+  O  <= (X xor Y) xor Ci;
   Co <= ((X xor Y) and Ci) or (X and Y);
 
 end;
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
index 1d255c9..38227a4 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
@@ -1,4 +1,4 @@
-----------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 -- Company:
 -- Engineer:
 --
@@ -16,7 +16,7 @@
 -- Revision 0.01 - File Created
 -- Additional Comments:
 --
-----------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 
 
 library IEEE;
@@ -50,35 +50,35 @@ begin
   buf(1) := Y;
   buf(2) := Ci;
 
-     case (buf) is
-      when "000" =>
-         O <= '0';
-         Co <= '0';
-      when "001" =>
-         O <= '1';
-         Co <= '0';
-      when "010" =>
-         O <= '1';
-         Co <= '0';
-      when "011" =>
-         O <= '0';
-         Co <= '1';
-      when "100" =>
-         O <= '1';
-         Co <= '0';
-      when "101" =>
-         O <= '0';
-         Co <= '1';
-      when "110" =>
-         O <= '0';
-         Co <= '1';
-      when "111" =>
-         O <= '1';
-         Co <= '1';
-      when others =>
-         O <= '0';
-         Co <= '0';
-   end case;
+  case (buf) is
+    when "000" =>
+      O  <= '0';
+      Co <= '0';
+    when "001" =>
+      O  <= '1';
+      Co <= '0';
+    when "010" =>
+      O  <= '1';
+      Co <= '0';
+    when "011" =>
+      O  <= '0';
+      Co <= '1';
+    when "100" =>
+      O  <= '1';
+      Co <= '0';
+    when "101" =>
+      O  <= '0';
+      Co <= '1';
+    when "110" =>
+      O  <= '0';
+      Co <= '1';
+    when "111" =>
+      O  <= '1';
+      Co <= '1';
+    when others =>
+      O  <= '0';
+      Co <= '0';
+  end case;
 
 end process Adder;
 
diff --git a/vhdl_ls.toml b/vhdl_ls.toml
index 79148f6..d481c37 100644
--- a/vhdl_ls.toml
+++ b/vhdl_ls.toml
@@ -2,15 +2,15 @@ standard = "2008"
 
 [libraries]
 defaultlib.files = [
-    "pb_APP_log_comb.sim/sim_1/behav/xsim/**/*.vhd",
+    "pb_APP_log_comb.srcs/**/*.vhd",
 ]
 defaultlib.exclude = [
-    "**/*.vdb", # compiled binaries
+    "**/*.vdb",       # compiled binaries
     "**/xsim.dir/**", # simulation-specific internal files
 ]
 
 UNISIM.files = [
-    "/opt/Xilinx/Vivado/2023.1/data/vhdl/src/unisims/unisim_VCOMP.vhd",
+    "/tools/Xilinx/Vivado/2020.2/data/vhdl/src/unisims/unisim_VCOMP.vhd",
 ]
 UNISIM.is_third_party = true