Merge branch 'master' of chausse.xyz:s4-app1

3 files changed, 87 insertions, 1 deletions

diff --git a/rapport/annexe.tex b/rapport/annexe.tex
new file mode 100644
index 0000000..f15f688
--- /dev/null
+++ b/rapport/annexe.tex
@@ -0,0 +1,18 @@
+\newpage
+\appendix
+\section{Code VHDL}
+
+\begin{figure}[H]
+  \tiny
+\centering
+\begin{varwidth}{\linewidth}
+  \input{assets/code/thermo2bin.tex}
+\end{varwidth}
+\caption{Module Thermo2bin}
+\end{figure}
+
+\section{Simulations}
+
+\section{Tables de Vérité et Karnaugh}
+
+
diff --git a/rapport/assets/code/thermo2bin.tex b/rapport/assets/code/thermo2bin.tex
new file mode 100644
index 0000000..b4e60a4
--- /dev/null
+++ b/rapport/assets/code/thermo2bin.tex
@@ -0,0 +1,63 @@
+\begin{verbatim}
+architecture Behavioral of Thermo2Bin is
+    signal first_segment_of_four : STD_LOGIC_VECTOR(3 downto 0);
+    signal second_segment_of_four : STD_LOGIC_VECTOR(3 downto 0);
+    signal third_segment_of_four : STD_LOGIC_VECTOR(3 downto 0);
+
+    component Add4Bits is
+        Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
+            B : in STD_LOGIC_VECTOR (3 downto 0);
+            C : in STD_LOGIC;
+            R : out STD_LOGIC_VECTOR (3 downto 0);
+            Rc : out STD_LOGIC);
+    end component;
+
+    signal first_plus_second : STD_LOGIC_VECTOR(3 downto 0);
+    signal carry_out_first_plus_second : STD_LOGIC;
+    signal last_carry_out : STD_LOGIC;
+
+begin
+    first_segment_of_four(3) <= '0';
+    first_segment_of_four(2) <= thermo_bus(11);
+    first_segment_of_four(1) <= NOT thermo_bus(11) AND thermo_bus(9);
+    first_segment_of_four(0) <= NOT thermo_bus(11) AND ((NOT thermo_bus(9) AND thermo_bus(8)) OR (thermo_bus(10) AND thermo_bus(9)));
+
+    second_segment_of_four(3) <= '0';
+    second_segment_of_four(2) <= thermo_bus(7);
+    second_segment_of_four(1) <= NOT thermo_bus(7) AND thermo_bus(5);
+    second_segment_of_four(0) <= NOT thermo_bus(7) AND ((NOT thermo_bus(5) AND thermo_bus(4)) OR (thermo_bus(6) AND thermo_bus(5)));
+
+    third_segment_of_four(3) <= '0';
+    third_segment_of_four(2) <= thermo_bus(3);
+    third_segment_of_four(1) <= NOT thermo_bus(3) AND thermo_bus(1);
+    third_segment_of_four(0) <= NOT thermo_bus(3) AND ((NOT thermo_bus(1) AND thermo_bus(0)) OR (thermo_bus(2) AND thermo_bus(1)));
+
+    first_plus_second_adder : Add4Bits port map (
+      A => first_segment_of_four,
+      B => second_segment_of_four,
+      R => first_plus_second,
+      Rc => carry_out_first_plus_second,
+      C => '0');
+
+    plus_third_adder : Add4Bits port map (
+      A => first_plus_second,
+      B => third_segment_of_four,
+      R => binary_out,
+      Rc => last_carry_out,
+      C => carry_out_first_plus_second);
+
+    error <= (
+    (thermo_bus(11) AND NOT thermo_bus(10)) OR
+    (thermo_bus(10) AND NOT thermo_bus(9)) OR
+    (thermo_bus(9)  AND NOT thermo_bus(8)) OR
+    (thermo_bus(8)  AND NOT thermo_bus(7)) OR
+    (thermo_bus(7)  AND NOT thermo_bus(6)) OR
+    (thermo_bus(6)  AND NOT thermo_bus(5)) OR
+    (thermo_bus(5)  AND NOT thermo_bus(4)) OR
+    (thermo_bus(4)  AND NOT thermo_bus(3)) OR
+    (thermo_bus(3)  AND NOT thermo_bus(2)) OR
+    (thermo_bus(2)  AND NOT thermo_bus(1)) OR
+    (thermo_bus(1)  AND NOT thermo_bus(0)));
+
+end Behavioral;
+\end{verbatim}
diff --git a/rapport/main.tex b/rapport/main.tex
index e181276..68cffbb 100644
--- a/rapport/main.tex
+++ b/rapport/main.tex
@@ -7,6 +7,8 @@
 \usepackage{booktabs}
 \usepackage{multicol}
 \usepackage{float}
+\usepackage{varwidth}
+% \usepackage[toc,page]{appendix}
 \usepackage[usenames,dvipsnames]{xcolor}
 
 \title{Rapport d'APP}
@@ -31,6 +33,9 @@
 
 \begin{document}
 \maketitle
+\newpage
+\tableofcontents
+\newpage
 
 \todo{test} \fixme{another test} \note{interesting} \question{wtf}
 
@@ -55,5 +60,5 @@ minimum de 2 Volts. Donc selon le 74V1T04STR, le NC7SP04P5X envoie toujours un n
 tout le temps allumé sauf lorsque le connecteur de test de la del est en mode de test car un bon niveau logique haut est envoyé à
 l'entrée des 74V1T04STR.
 
-
+\input{annexe.tex}
 \end{document}