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| author | Benjamin Chausse <benjamin@chausse.xyz> | 2025-05-03 15:31:02 -0400 |
|---|---|---|
| committer | Benjamin Chausse <benjamin@chausse.xyz> | 2025-05-03 15:31:02 -0400 |
| commit | feb78868167b4543c2ce87643f54761fea721605 (patch) | |
| tree | 24675a9f5d3e2abd972cd491f9b932ca4de14d4d | |
| parent | 1b8b70ea0d1f1dd79a1b1f1a1b05208bb8c1ca30 (diff) | |
Follow instructions for parity check
| -rw-r--r-- | pb_APP_log_comb.ip_user_files/README.txt | 1 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/new/parity_check.vhd (renamed from pb_APP_log_comb.srcs/sources_1/new/is_even.vhd) | 39 | ||||
| -rw-r--r-- | pb_APP_log_comb.xpr | 2 |
3 files changed, 30 insertions, 12 deletions
diff --git a/pb_APP_log_comb.ip_user_files/README.txt b/pb_APP_log_comb.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/pb_APP_log_comb.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd b/pb_APP_log_comb.srcs/sources_1/new/parity_check.vhd index 53eb4dc..50ffdfa 100644 --- a/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd +++ b/pb_APP_log_comb.srcs/sources_1/new/parity_check.vhd @@ -2,9 +2,9 @@ -- Company: -- Engineer: -- --- Create Date: 05/03/2025 12:04:25 PM +-- Create Date: 05/03/2025 03:20:01 PM -- Design Name: --- Module Name: is_even - Behavioral +-- Module Name: parity_check - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: @@ -31,19 +31,36 @@ use IEEE.STD_LOGIC_1164.ALL; --library UNISIM; --use UNISIM.VComponents.all; -entity is_even is - Port ( x : in STD_LOGIC_VECTOR (3 downto 0); - o : out STD_LOGIC); -end is_even; +entity parity_check is + Port ( ADCbin : in STD_LOGIC_VECTOR (3 downto 0); + S1 : in STD_LOGIC; + Parite : out STD_LOGIC); +end parity_check; -architecture Behavioral of is_even is +architecture Behavioral of parity_check is - signal y : STD_LOGIC_VECTOR (0 to 1); + signal Y : STD_LOGIC_VECTOR (2 downto 0); + signal PreFlip : STD_LOGIC; begin - y(0) <= x(0) xor x(1); - y(1) <= x(2) xor x(3); - o <= y(0) xor y(1); + Y(0) <= ADCbin(0) xor ADCbin(1); + Y(1) <= ADCbin(2) xor ADCbin(3); + Y(2) <= Y(0) xor Y(1); + + flipCheck : process(Y, S1) + begin + + case (S1) is + when '0' => + Parite <= Y(2); + when '1' => + Parite <= not Y(2); + when others => + Parite <= '0'; + end case; + + end process; + end Behavioral; diff --git a/pb_APP_log_comb.xpr b/pb_APP_log_comb.xpr index f95dd3a..520cba0 100644 --- a/pb_APP_log_comb.xpr +++ b/pb_APP_log_comb.xpr @@ -143,7 +143,7 @@ <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PSRCDIR/sources_1/new/is_even.vhd"> + <File Path="$PSRCDIR/sources_1/new/parity_check.vhd"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> |