rollback septseg to 4 bits

3 files changed, 45 insertions, 46 deletions

diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd
index d2043c4..2129009 100644
--- a/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd
@@ -56,8 +56,8 @@ architecture BEHAVIORAL of AppCombi_top is
   signal d_sum       : std_logic_vector (4 downto 0):= "00000";   -- somme

   signal d_cout      : std_logic := '0';             -- retenue sortie

   --

-  signal d_AFF0      : std_logic_vector (4 downto 0):= "00000";

-  signal d_AFF1      : std_logic_vector (4 downto 0):= "00000";

+  signal d_AFF0      : std_logic_vector (3 downto 0):= "0000";

+  signal d_AFF1      : std_logic_vector (3 downto 0):= "0000";

   --

   signal ADCbin      : std_logic_vector (3 downto 0) := "0000";

   signal error       : std_logic := '0';

@@ -66,13 +66,13 @@ architecture BEHAVIORAL of AppCombi_top is
   --

   signal parite_out  : std_logic := '0';

 

-  component parity_check is Port ( 

+  component parity_check is Port (

     ADCbin : in STD_LOGIC_VECTOR (3 downto 0);

     S1 : in STD_LOGIC;

     Parite : out STD_LOGIC);

   end component;

 

-  component Fct_2_3 is Port ( 

+  component Fct_2_3 is Port (

     ADCbin : in STD_LOGIC_VECTOR (3 downto 0);

     A2_3 : out STD_LOGIC_VECTOR (2 downto 0));

   end component;

@@ -82,7 +82,7 @@ architecture BEHAVIORAL of AppCombi_top is
     bus_out : out STD_LOGIC_VECTOR (7 downto 0));

   end component;

 

-  component Thermo2Bin is Port ( 

+  component Thermo2Bin is Port (

     thermo_bus : in STD_LOGIC_VECTOR (11 downto 0);

     binary_out : out STD_LOGIC_VECTOR (3 downto 0);

     error : out STD_LOGIC);

@@ -107,8 +107,8 @@ architecture BEHAVIORAL of AppCombi_top is
 

   component septSegments_Top is Port (

     clk          : in   STD_LOGIC;                      -- horloge systeme, typique 100 MHz (preciser par le constante)

-    i_AFF0       : in   STD_LOGIC_VECTOR (4 downto 0);  -- donnee a afficher sur 8 bits : chiffre hexa position 1 et 0

-    i_AFF1       : in   STD_LOGIC_VECTOR (4 downto 0);  -- donnee a afficher sur 8 bits : chiffre hexa position 1 et 0

+    i_AFF0       : in   STD_LOGIC_VECTOR (3 downto 0);  -- donnee a afficher sur 8 bits : chiffre hexa position 1 et 0

+    i_AFF1       : in   STD_LOGIC_VECTOR (3 downto 0);  -- donnee a afficher sur 8 bits : chiffre hexa position 1 et 0

     o_AFFSSD_Sim : out string(1 to 2);

     o_AFFSSD     : out  STD_LOGIC_VECTOR (7 downto 0)

   );

@@ -140,7 +140,7 @@ begin
     binary_out => ADCbin,

     error => error

   );

-  

+

   ----------------------------------------

   -- PMOD DELs

   ----------------------------------------

@@ -148,25 +148,25 @@ begin
     ADCbin => ADCbin,

     A2_3 => A2_3

   );

-  

+

   to_pmod : Decodeur_3_8 port map (

     control_bits => A2_3,

     bus_out => o_pmodled

   );

-  

+

   ----------------------------------------

   -- Parite

   ----------------------------------------

   parity : parity_check port map (

     ADCbin => ADCbin,

     S1 => button_s1,

-    Parite => parite_out 

+    Parite => parite_out

   );

-  

+

   DEL2 <= parite_out;

   o_led(0) <= parite_out;

-  

-  

+

+

   adder4 : Add4Bits port map (

     A => d_opa,

     B => d_opb,

@@ -181,12 +181,10 @@ begin
   d_opb         <=  i_btn; -- operande B sur boutons

   d_cin         <=  '0';   -- la retenue d'entrée alterne 0 1 a 1 Hz

 

-  d_AFF0        <=  ADCth(11 downto 7);--d_sum(4 downto 0);        -- Le resultat de votre additionneur affiché sur PmodSSD(0)

-  d_AFF1        <=  ADCth(6 downto 2); --'0' & '0' & '0' & '0' & d_Cout; -- La retenue de sortie affichée sur PmodSSD(1) (0 ou 1)

+  -- d_AFF0        <=  ADCth(11 downto 7);--d_sum(4 downto 0);        -- Le resultat de votre additionneur affiché sur PmodSSD(0)

+  -- d_AFF1        <=  ADCth(6 downto 2); --'0' & '0' & '0' & '0' & d_Cout; -- La retenue de sortie affichée sur PmodSSD(1) (0 ou 1)

   o_led6_r      <=  d_Cout;                   -- La led couleur représente aussi la retenue en sortie  Cout

   --o_pmodled       <=  d_opa & d_opb;          -- Les opérandes d'entrés reproduits combinés sur Pmod8LD

   --o_led (3 downto 0)  <=  '0' & '0' & '0' & d_S_1Hz;   -- La LED0 sur la carte représente la retenue d'entrée

 

 end BEHAVIORAL;

-

-

diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_Top.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_Top.vhd
index 369248c..0b89a26 100644
--- a/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_Top.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_Top.vhd
@@ -46,8 +46,8 @@ use ieee.std_logic_unsigned.all;
 entity septSegments_Top is

 generic (const_CLK_MHz: integer := 100);                     -- horloge en MHz, typique 100 MHz

     Port (   clk            : in   STD_LOGIC;                      -- horloge systeme, typique 100 MHz (preciser par le constante)

-             i_AFF0         : in   STD_LOGIC_VECTOR (4 downto 0);  -- donnee a afficher sur 4 bits : chiffre hexa position 0

-             i_AFF1         : in   STD_LOGIC_VECTOR (4 downto 0);  -- donnee a afficher sur 4 bits : chiffre hexa position 1

+             i_AFF0         : in   STD_LOGIC_VECTOR (3 downto 0);  -- donnee a afficher sur 4 bits : chiffre hexa position 0

+             i_AFF1         : in   STD_LOGIC_VECTOR (3 downto 0);  -- donnee a afficher sur 4 bits : chiffre hexa position 1

              o_AFFSSD_Sim   : out string(2 downto 1);

              o_AFFSSD       : out  STD_LOGIC_VECTOR (7 downto 0)

            );

@@ -57,7 +57,7 @@ architecture Behavioral of septSegments_Top is
 

 component septSegments_encodeur is

 Port(

-         i_AFF : in  STD_LOGIC_VECTOR(4 downto 0); -- caractère à afficher

+         i_AFF : in  STD_LOGIC_VECTOR(3 downto 0); -- caractère à afficher

          o_CharacterePourSim : out string(1 to 1);        -- pour simulation seulement

          o_Seg : out STD_LOGIC_VECTOR(6 downto 0) -- encodage 7-segments

     );

diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_encodeur.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_encodeur.vhd
index 13f4ca0..3c56c01 100644
--- a/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_encodeur.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/imports/src/septSegments_encodeur.vhd
@@ -42,7 +42,7 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

 

 entity septSegments_encodeur is Port(

-  i_AFF : in  STD_LOGIC_VECTOR(4 downto 0); -- caractère à afficher

+  i_AFF : in  STD_LOGIC_VECTOR(3 downto 0); -- caractère à afficher

   o_CharacterePourSim : out string(1 to 1);    -- pour simulation seulement

   o_Seg : out STD_LOGIC_VECTOR(6 downto 0)); -- encodage 7-segments

 end septSegments_encodeur;

@@ -53,7 +53,7 @@ architecture Behavioral of septSegments_encodeur is
   function segment2String(display : std_logic_vector( 6 downto 0))

     return string is variable v_ReturnString : string(1 to 1);

     begin

-    case display is

+		case display is

       when "0111111" => v_ReturnString := "0"; -- 0

       when "0000110" => v_ReturnString := "1"; -- 1

       when "1011011" => v_ReturnString := "2"; -- 2

@@ -71,9 +71,10 @@ architecture Behavioral of septSegments_encodeur is
       when "1111001" => v_ReturnString := "E"; -- E

       when "1110001" => v_ReturnString := "F"; -- F

       when "1000000" => v_ReturnString := "-"; -- négatif

-      when "1010000" => v_ReturnString := "r"; -- r pour erreur

-      when others  => v_ReturnString := "_"; -- code non reconnu

-    end case;

+			when "1010000" => v_ReturnString := "r"; -- r pour erreur

+      when others    => v_ReturnString := "_"; -- code non reconnu

+		end case;

+

     return v_ReturnString;

   end segment2String;

 

@@ -86,26 +87,26 @@ begin
   begin

     case i_AFF is

       --                       "gfedcba"

-      when "00000" => s_Seg <= "0111111"; -- 0

-      when "00001" => s_Seg <= "0000110"; -- 1

-      when "00010" => s_Seg <= "1011011"; -- 2

-      when "00011" => s_Seg <= "1001111"; -- 3

-      when "00100" => s_Seg <= "1100110"; -- 4

-      when "00101" => s_Seg <= "1101101"; -- 5

-      when "00110" => s_Seg <= "1111101"; -- 6

-      when "00111" => s_Seg <= "0000111"; -- 7

-      when "01000" => s_Seg <= "1111111"; -- 8

-      when "01001" => s_Seg <= "1101111"; -- 9

-      when "01010" => s_Seg <= "1110111"; -- A

-      when "01011" => s_Seg <= "1111100"; -- B

-      when "01100" => s_Seg <= "0111001"; -- C

-      when "01101" => s_Seg <= "1011110"; -- D

-      when "01110" => s_Seg <= "1111001"; -- E

-      when "01111" => s_Seg <= "1110001"; -- F

-      when "10000" => s_Seg <= "1000000"; -- neg. (-)

-      when "10001" => s_Seg <= "1010000"; -- Err. (r)

-      when "10010" => s_Seg <= "0001000"; -- invalid (_)

-      when others  => s_Seg <= "0000000";

+      when "0000" => s_Seg <= "0111111"; -- 0

+      when "0001" => s_Seg <= "0000110"; -- 1

+      when "0010" => s_Seg <= "1011011"; -- 2

+      when "0011" => s_Seg <= "1001111"; -- 3

+      when "0100" => s_Seg <= "1100110"; -- 4

+      when "0101" => s_Seg <= "1101101"; -- 5

+      when "0110" => s_Seg <= "1111101"; -- 6

+      when "0111" => s_Seg <= "0000111"; -- 7

+      when "1000" => s_Seg <= "1111111"; -- 8

+      when "1001" => s_Seg <= "1101111"; -- 9

+      when "1010" => s_Seg <= "1110111"; -- A

+      when "1011" => s_Seg <= "1111100"; -- B

+      when "1100" => s_Seg <= "0111001"; -- C

+      -- when "1101" => s_Seg <= "1011110"; -- D

+      -- when "1110" => s_Seg <= "1111001"; -- E

+      -- when "1111" => s_Seg <= "1110001"; -- F

+      when "1101" => s_Seg <= "1000000"; -- neg. (-)

+      when "1110" => s_Seg <= "1010000"; -- Err. (r)

+      when "1111" => s_Seg <= "0001000"; -- undefined (_)

+      when others  => s_Seg <= "0001000";

     end case;

   end process;