unit test add 4 bit, Fix Add1bitB

4 files changed, 80 insertions, 22 deletions

diff --git a/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd
index 0023bdc..2ce3253 100644
--- a/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd
+++ b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd
@@ -70,6 +70,21 @@ end COMPONENT;
    signal vecteur_test_sim   :  STD_LOGIC_VECTOR (13 DOWNTO 0) := (others => '0');

    signal resultat_attendu       :  STD_LOGIC_VECTOR (4 DOWNTO 0) := "00000";

 

+COMPONENT Add4Bits

+    PORT (

+        A  : in  STD_LOGIC_VECTOR(3 downto 0);

+        B  : in  STD_LOGIC_VECTOR(3 downto 0);

+        C  : in  STD_LOGIC;

+        R  : out STD_LOGIC_VECTOR(3 downto 0);

+        Rc : out STD_LOGIC

+    );

+END COMPONENT;

+    

+    signal add_a_sim  : STD_LOGIC_VECTOR(3 downto 0) := "0000";

+    signal add_b_sim  : STD_LOGIC_VECTOR(3 downto 0) := "0000";

+    signal add_cin_sim : STD_LOGIC := '0';

+    signal add_result_sim : STD_LOGIC_VECTOR(3 downto 0);

+    signal add_cout_sim : STD_LOGIC;

 

    constant sysclk_Period  : time := 8 ns;

    

@@ -84,9 +99,13 @@ end COMPONENT;
   --  vecteur de test è modifier selon les besoins

   --  res      op_a     op_b    cin

     "00000" & "0000" & "0000" & '0',  --   0 +  0  

-    "00000" & "0000" & "0001" & '0',  --   0 +  1 

+    "00001" & "0000" & "0001" & '0',  --   0 +  1 

     -- modifez et/ou ajoutez vos valeurs

-  

+    "00001" & "0000" & "0000" & '1',  --   carry in

+    "01111" & "0000" & "1111" & '0',  --   0 +  F

+    "01111" & "1111" & "0000" & '0',  --   F +  0

+    

+    

     -- conserver la ligne ci-bas.

     others => "00000" & "0000" & "0000" & '0'  --  0 + 0 

     );

@@ -94,6 +113,14 @@ end COMPONENT;
 

 begin

 

+uut_add4bits: Add4Bits

+    PORT MAP (

+        A  => add_a_sim,

+        B  => add_b_sim,

+        C  => add_cin_sim,

+        R  => add_result_sim,

+        Rc => add_cout_sim

+    );

 

 -- Pattes du FPGA Zybo-Z7

 uut: AppCombi_top

@@ -140,12 +167,41 @@ uut: AppCombi_top
               btn_sim <= vecteur_test_sim (4 downto 1) ;

               cin_sim <= vecteur_test_sim (0);

 			  resultat_attendu <= vecteur_test_sim(13 downto 9);

+			  

+			  -- Assignation of variables to add4bit

+			  add_a_sim     <= vecteur_test_sim(8 downto 5);

+              add_b_sim     <= vecteur_test_sim(4 downto 1);

+              add_cin_sim   <= vecteur_test_sim(0);   

+			  

               wait for delai_sim;

-			  --assert (resultat_attendu /= (probe_adder_result) ) report "Resultat pas celui prévu." severity warning; 

+

+              -- Optional: Compare results

+              assert (resultat_attendu(3 downto 0) = add_result_sim)

+                report "Add4Bits: Somme incorrecte. Attendu = " &

+                    integer'image(to_integer(unsigned(resultat_attendu(3 downto 0)))) &

+                    ", Obtenu = " &

+                    integer'image(to_integer(unsigned(add_result_sim))) &

+                    ", A = " &

+                    integer'image(to_integer(unsigned(add_a_sim(3 downto 0)))) &

+                    ", B = " &

+                    integer'image(to_integer(unsigned(add_b_sim(3 downto 0))))

+                severity warning;

+

+              assert (resultat_attendu(4) = add_cout_sim)

+                report "Add4Bits: Retenue incorrecte. Attendu = '" &

+                    std_logic'image(resultat_attendu(4)) &

+                    "', Obtenu = '" &

+                    std_logic'image(add_cout_sim) & "'" &

+                    ", A = " &

+                    integer'image(to_integer(unsigned(add_a_sim(3 downto 0)))) &

+                    ", B = " &

+                    integer'image(to_integer(unsigned(add_b_sim(3 downto 0))))

+                severity warning;

+

               table_valeurs_adr := table_valeurs_adr + 1;

-			  if(table_valeurs_adr = 63) then

-				exit;

-			  end if;

+              if(table_valeurs_adr = 63) then

+                exit;

+              end if;

          end loop; 

            

          WAIT; -- will wait forever

diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
index 5f99927..1d255c9 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
@@ -41,15 +41,14 @@ end Add1BitB;
 
 architecture Behavioral of Add1BitB is
 
-  signal buf: STD_LOGIC_VECTOR(2 downto 0);
-
 begin
 
 Adder: process(X, Y, Ci) is
+  variable buf: STD_LOGIC_VECTOR(2 downto 0);
 begin
-  buf(0) <= X;
-  buf(1) <= Y;
-  buf(2) <= Ci;
+  buf(0) := X;
+  buf(1) := Y;
+  buf(2) := Ci;
 
      case (buf) is
       when "000" =>
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
index 71c09d9..75c6cab 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
@@ -67,7 +67,7 @@ architecture Behavioral of Add4Bits is
 
 begin
 
-  first : Add1BitA port map (
+  first : Add1BitB port map (
     X  => A(0),
     Y  => B(0),
     Ci => C,
@@ -75,7 +75,7 @@ begin
     Co => bufA
   );
 
-  sec : Add1BitA port map (
+  sec : Add1BitB port map (
     X  => A(1),
     Y  => B(1),
     Ci => bufA,
@@ -83,7 +83,7 @@ begin
     Co => bufB
   );
 
-  third : Add1BitB port map (
+  third : Add1BitA port map (
     X  => A(2),
     Y  => B(2),
     Ci => bufB,
@@ -91,7 +91,7 @@ begin
     Co => bufC
   );
 
-  fourth : Add1BitB port map (
+  fourth : Add1BitA port map (
     X  => A(3),
     Y  => B(3),
     Ci => bufC,
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd b/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd
index e0cb89c..470e7c4 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd
@@ -35,13 +35,14 @@ use IEEE.STD_LOGIC_1164.ALL;
 
 entity Fct_2_3 is
     Port ( ADCbin : in STD_LOGIC_VECTOR (3 downto 0);
-           A2_3 : out STD_LOGIC_VECTOR (2 downto 0));
+           A2_3 : out STD_LOGIC_VECTOR (3 downto 0));
 end Fct_2_3;
 
 architecture Behavioral of Fct_2_3 is
     signal shifted_once : STD_LOGIC_VECTOR(3 downto 0);
     signal shifted_twice : STD_LOGIC_VECTOR(3 downto 0);
     signal shifted_thrice : STD_LOGIC_VECTOR(3 downto 0);
+    signal carry_out : STD_LOGIC;
     
     component Add4Bits is
     Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
@@ -52,16 +53,18 @@ architecture Behavioral of Fct_2_3 is
     end component;
 begin
     -- N x 2^-1 : shifted once
-    shifted_once <= '0' & ADCbin(3 downto 0);
+    shifted_once <= '0' & ADCbin(3 downto 1);
 
     -- N x 2^-3 : shifted thrice
-    shifted_twice <= '0' & shifted_once(3 downto 0);
-    shifted_thrice <= '0' & shifted_twice(3 downto 0);
+    shifted_twice <= '0' & shifted_once(3 downto 1);
+    shifted_thrice <= '0' & shifted_twice(3 downto 1);
     
     -- Both are then added to give the result of the 2/3 multiplication (0.625)
     result : Add4Bits port map (
-        X  => shifted_once,
-        Y  => shifted_thrice,
-        O => A2_3
+        A  => "0110",
+        B  => "0001",
+        C => '0',
+        R => A2_3,
+        Rc => carry_out
     );
 end Behavioral;