diff options
| -rw-r--r-- | pb_APP_log_comb.hw/hw_1/hw.xml | 17 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd | 13 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd | 6 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/new/is_even.vhd | 49 | ||||
| -rw-r--r-- | pb_APP_log_comb.xpr | 8 |
5 files changed, 85 insertions, 8 deletions
diff --git a/pb_APP_log_comb.hw/hw_1/hw.xml b/pb_APP_log_comb.hw/hw_1/hw.xml new file mode 100644 index 0000000..1880a36 --- /dev/null +++ b/pb_APP_log_comb.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> + +<hwsession version="1" minor="2"> + <device name="xc7z010_1" gui_info=""/> + <ObjectList object_type="hw_device" gui_info=""> + <Object name="xc7z010_1" gui_info=""> + <Properties Property="FULL_PROBES.FILE" value=""/> + <Properties Property="PROBES.FILE" value=""/> + <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/AppCombi_top.bit"/> + <Properties Property="SLR.COUNT" value="1"/> + </Object> + </ObjectList> + <probeset name="hw project" active="false"/> +</hwsession> diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd index 79209c9..b9be1dc 100644 --- a/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd +++ b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd @@ -56,10 +56,10 @@ architecture BEHAVIORAL of AppCombi_top is component Add4Bits is Port (
- A : in STD_LOGIC_VECTOR (0 to 3);
- B : in STD_LOGIC_VECTOR (0 to 3);
+ A : in STD_LOGIC_VECTOR (3 downto 0);
+ B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC;
- R : out STD_LOGIC_VECTOR (0 to 3);
+ R : out STD_LOGIC_VECTOR (3 downto 0);
Rc : out STD_LOGIC
);
end component;
@@ -114,6 +114,13 @@ begin o_pmodled <= d_opa & d_opb; -- Les opérandes d'entrés reproduits combinés sur Pmod8LD
o_led (3 downto 0) <= '0' & '0' & '0' & d_S_1Hz; -- La LED0 sur la carte représente la retenue d'entrée
+adder4 : Add4Bits port map (
+ A => d_opa,
+ B => d_opb,
+ C => d_cin,
+ R => d_sum,
+ Rc => d_cout
+);
end BEHAVIORAL;
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd index 371d81b..71c09d9 100644 --- a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd +++ b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd @@ -32,10 +32,10 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; entity Add4Bits is - Port ( A : in STD_LOGIC_VECTOR (0 to 3); - B : in STD_LOGIC_VECTOR (0 to 3); + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); C : in STD_LOGIC; - R : out STD_LOGIC_VECTOR (0 to 3); + R : out STD_LOGIC_VECTOR (3 downto 0); Rc : out STD_LOGIC); end Add4Bits; diff --git a/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd b/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd new file mode 100644 index 0000000..53eb4dc --- /dev/null +++ b/pb_APP_log_comb.srcs/sources_1/new/is_even.vhd @@ -0,0 +1,49 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 05/03/2025 12:04:25 PM +-- Design Name: +-- Module Name: is_even - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity is_even is + Port ( x : in STD_LOGIC_VECTOR (3 downto 0); + o : out STD_LOGIC); +end is_even; + +architecture Behavioral of is_even is + + signal y : STD_LOGIC_VECTOR (0 to 1); + +begin + + y(0) <= x(0) xor x(1); + y(1) <= x(2) xor x(3); + o <= y(0) xor y(1); + +end Behavioral; diff --git a/pb_APP_log_comb.xpr b/pb_APP_log_comb.xpr index d24bc05..f95dd3a 100644 --- a/pb_APP_log_comb.xpr +++ b/pb_APP_log_comb.xpr @@ -227,7 +227,9 @@ <Runs Version="1" Minor="15"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/tetm2701/Documents/Repos/git_gen420430A-circuits-combinatoires/Ressources/Vivado/pb_APP_log_comb/pb_APP_log_comb.srcs/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"> + <Desc>Vivado Synthesis Defaults</Desc> + </StratHandle> <Step Id="synth_design"/> </Strategy> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> @@ -237,7 +239,9 @@ </Run> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/tetm2701/Documents/Repos/git_gen420430A-circuits-combinatoires/Ressources/Vivado/pb_APP_log_comb/pb_APP_log_comb.srcs/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"> + <Desc>Default settings for Implementation.</Desc> + </StratHandle> <Step Id="init_design"/> <Step Id="opt_design"/> <Step Id="power_opt_design"/> |