summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--Readme.md4
-rw-r--r--pb_APP_log_comb.srcs/sources_1/new/Bin2DualBCD_NS.vhd4
-rw-r--r--pb_APP_log_comb.srcs/sources_1/new/Bin2DualBCD_S.vhd81
3 files changed, 85 insertions, 4 deletions
diff --git a/Readme.md b/Readme.md
index 7eff830..e10f87e 100644
--- a/Readme.md
+++ b/Readme.md
@@ -9,8 +9,8 @@
- [x] Faire le Testbench
- [ ] Bin2DualBCD
- [x] Bin2DualBCD_NS
- - [ ] Moins_5
- - [ ] Bin2DualBCD_S
+ - [x] Moins_5
+ - [x] Bin2DualBCD_S
- [ ] Mux
- [x] septSegments_Top
- [ ] Diviseur d’horloge : synchro_module_v2
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Bin2DualBCD_NS.vhd b/pb_APP_log_comb.srcs/sources_1/new/Bin2DualBCD_NS.vhd
index ff56333..34c101f 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Bin2DualBCD_NS.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Bin2DualBCD_NS.vhd
@@ -93,8 +93,8 @@ begin
units_out <= "0101";
dizaines_out <= "0001";
when others =>
- units_out <= "0000";
- dizaines_out <= "0000";
+ units_out <= "1111";
+ dizaines_out <= "1110";
end case;
end process;
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Bin2DualBCD_S.vhd b/pb_APP_log_comb.srcs/sources_1/new/Bin2DualBCD_S.vhd
new file mode 100644
index 0000000..8f01c36
--- /dev/null
+++ b/pb_APP_log_comb.srcs/sources_1/new/Bin2DualBCD_S.vhd
@@ -0,0 +1,81 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 05/05/2025 02:21:36 PM
+-- Design Name:
+-- Module Name: Bin2DualBCD_S - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Bin2DualBCD_S is
+ Port ( signed_in : in STD_LOGIC_VECTOR (3 downto 0);
+ signed_code : out STD_LOGIC_VECTOR (3 downto 0);
+ signed_units : out STD_LOGIC_VECTOR (3 downto 0));
+end Bin2DualBCD_S;
+
+architecture Behavioral of Bin2DualBCD_S is
+
+begin
+
+ process (signed_in(0))
+ begin
+ case (signed_in(0)) is
+ when '0' =>
+ signed_code <= "0000";
+ when '1' =>
+ signed_code <= "1101";
+ when others =>
+ signed_code <= "1110"; -- E
+ end case;
+ end process;
+
+ -- Units are the same regardless of sign.
+ process (signed_in(2 downto 0))
+ begin
+ case (signed_in(2 downto 0)) is
+ when "000" =>
+ signed_units <= "0000";
+ when "001" =>
+ signed_units <= "0001";
+ when "010" =>
+ signed_units <= "0010";
+ when "011" =>
+ signed_units <= "0011";
+ when "100" =>
+ signed_units <= "0100";
+ when "101" =>
+ signed_units <= "0101";
+ when "110" =>
+ signed_units <= "0101";
+ when "111" =>
+ signed_units <= "0111";
+ when others =>
+ signed_units <= "1111"; -- r
+ end case;
+ end process;
+
+end Behavioral;