1 files changed, 72 insertions, 17 deletions
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
index be2cf13..371d81b 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
@@ -1,21 +1,21 @@
 ----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
+-- Company:
+-- Engineer:
+--
 -- Create Date: 04/30/2025 03:19:19 PM
--- Design Name: 
+-- Design Name:
 -- Module Name: Add4Bits - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
 -- Revision:
 -- Revision 0.01 - File Created
 -- Additional Comments:
--- 
+--
 ----------------------------------------------------------------------------------
 
 
@@ -32,16 +32,71 @@ use IEEE.STD_LOGIC_1164.ALL;
 --use UNISIM.VComponents.all;
 
 entity Add4Bits is
-    Port ( X : in STD_LOGIC_VECTOR (0 to 3);
-           Y : in STD_LOGIC_VECTOR (0 to 3);
-           Ci : in STD_LOGIC;
-           O : out STD_LOGIC_VECTOR (0 to 3);
-           Co : out STD_LOGIC);
+    Port ( A : in STD_LOGIC_VECTOR (0 to 3);
+           B : in STD_LOGIC_VECTOR (0 to 3);
+           C : in STD_LOGIC;
+           R : out STD_LOGIC_VECTOR (0 to 3);
+           Rc : out STD_LOGIC);
 end Add4Bits;
 
 architecture Behavioral of Add4Bits is
 
+  signal bufA : STD_LOGIC;
+  signal bufB : STD_LOGIC;
+  signal bufC : STD_LOGIC;
+
+  component Add1BitA is
+    Port (
+     X : in STD_LOGIC;
+     Y : in STD_LOGIC;
+     Ci: in STD_LOGIC;
+     O : out STD_LOGIC;
+     Co: out STD_LOGIC
+  );
+  end component;
+
+  component Add1BitB is
+    Port (
+     X : in STD_LOGIC;
+     Y : in STD_LOGIC;
+     Ci: in STD_LOGIC;
+     O : out STD_LOGIC;
+     Co: out STD_LOGIC
+  );
+  end component;
+
 begin
 
+  first : Add1BitA port map (
+    X  => A(0),
+    Y  => B(0),
+    Ci => C,
+    O => R(0),
+    Co => bufA
+  );
+
+  sec : Add1BitA port map (
+    X  => A(1),
+    Y  => B(1),
+    Ci => bufA,
+    O => R(1),
+    Co => bufB
+  );
+
+  third : Add1BitB port map (
+    X  => A(2),
+    Y  => B(2),
+    Ci => bufB,
+    O => R(2),
+    Co => bufC
+  );
+
+  fourth : Add1BitB port map (
+    X  => A(3),
+    Y  => B(3),
+    Ci => bufC,
+    O => R(3),
+    Co => Rc
+  );
 
 end Behavioral;