diff options
Diffstat (limited to 'pb_APP_log_comb.srcs')
| -rw-r--r-- | pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd | 70 | ||||
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd | 12 |
2 files changed, 76 insertions, 6 deletions
diff --git a/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd index 24a04c8..8350174 100644 --- a/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd +++ b/pb_APP_log_comb.srcs/sim_1/imports/verif/AppCombi_top_tb.vhd @@ -86,6 +86,16 @@ END COMPONENT; signal add_result_sim : STD_LOGIC_VECTOR(3 downto 0);
signal add_cout_sim : STD_LOGIC;
+COMPONENT Fct_2_3 is
+ Port ( ADCbin : in STD_LOGIC_VECTOR (3 downto 0);
+ A2_3 : out STD_LOGIC_VECTOR (2 downto 0));
+END COMPONENT;
+
+ signal fct_input_sim : STD_LOGIC_VECTOR(3 downto 0) := "0000";
+ signal fct_output_sim : STD_LOGIC_VECTOR(2 downto 0) := "000";
+ signal fct_vecteur_test_sim : STD_LOGIC_VECTOR (6 DOWNTO 0) := (others => '0');
+ signal fct_resultat_attendu : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
+
constant sysclk_Period : time := 8 ns;
@@ -114,6 +124,30 @@ END COMPONENT; others => "00000" & "0000" & "0000" & '0' -- 0 + 0
);
----------------------------------------------------------------------------
+-- Tableau pour tester les valeurs du module FCT
+----------------------------------------------------------------------------
+ type fct_table_valeurs_tests is array (integer range 0 to 13) of std_logic_vector(6 downto 0);
+ constant fct_mem_valeurs_tests : fct_table_valeurs_tests :=
+ (
+ -- vecteur de test è modifier selon les besoins
+ -- res input
+ "000" & "0000", -- 0
+ "000" & "0001", -- 1
+ "001" & "0010",
+ "001" & "0011",
+ "010" & "0100",
+ "011" & "0101",
+ "011" & "0110",
+ "011" & "0111",
+ "101" & "1000",
+ "101" & "1001",
+ "110" & "1010",
+ "110" & "1011",
+ "111" & "1100", -- 12
+ -- conserver la ligne ci-bas.
+ others => "000" & "0000" -- 0 + 0
+ );
+----------------------------------------------------------------------------
begin
@@ -125,6 +159,12 @@ uut_add4bits: Add4Bits R => add_result_sim,
Rc => add_cout_sim
);
+
+uut_fct_2_3: Fct_2_3
+ PORT MAP (
+ ADCbin => fct_input_sim,
+ A2_3 => fct_output_sim
+ );
-- Pattes du FPGA Zybo-Z7
uut: AppCombi_top
@@ -159,10 +199,11 @@ uut: AppCombi_top tb : PROCESS
variable delai_sim : time := 50 ns;
variable table_valeurs_adr : integer range 0 to 63;
+ variable fct_table_valeurs_adr : integer range 0 to 13;
BEGIN
+
-- Phase 1
- wait for delai_sim;
table_valeurs_adr := 0;
-- simuler une sequence de valeurs a l'entree
for index in 0 to mem_valeurs_tests'length-1 loop
@@ -179,7 +220,7 @@ uut: AppCombi_top wait for delai_sim;
- -- Optional: Compare results
+ -- Compare results. Des impression dans le terminal sont fait uniquement lors d'erreurs.
assert (resultat_attendu(3 downto 0) = add_result_sim)
report "Add4Bits: Somme incorrecte. Attendu = " &
integer'image(to_integer(unsigned(resultat_attendu(3 downto 0)))) &
@@ -206,6 +247,31 @@ uut: AppCombi_top if(table_valeurs_adr = 63) then
exit;
end if;
+ end loop;
+
+ -- Phase 2: Test de la fonction de multiplication 2/3
+ fct_table_valeurs_adr := 0;
+ for index in 0 to fct_mem_valeurs_tests'length-1 loop
+ fct_vecteur_test_sim <= fct_mem_valeurs_tests(fct_table_valeurs_adr);
+ fct_resultat_attendu <= fct_vecteur_test_sim(6 downto 4);
+ fct_input_sim <= fct_vecteur_test_sim(3 downto 0);
+
+ wait for delai_sim;
+
+ -- Comparation des resultats.
+ assert (fct_resultat_attendu(2 downto 0) = fct_output_sim)
+ report "FCT_2_3: Multiplication incorrecte. Attendu = " &
+ integer'image(to_integer(unsigned(fct_resultat_attendu))) &
+ ", Obtenu = " &
+ integer'image(to_integer(unsigned(fct_output_sim))) &
+ ", Avec = " &
+ integer'image(to_integer(unsigned(fct_input_sim)))
+ severity warning;
+
+ fct_table_valeurs_adr := fct_table_valeurs_adr + 1;
+ if(fct_table_valeurs_adr = 63) then
+ exit;
+ end if;
end loop;
WAIT; -- will wait forever
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd b/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd index 470e7c4..d1513fa 100644 --- a/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd +++ b/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd @@ -35,7 +35,7 @@ use IEEE.STD_LOGIC_1164.ALL; entity Fct_2_3 is Port ( ADCbin : in STD_LOGIC_VECTOR (3 downto 0); - A2_3 : out STD_LOGIC_VECTOR (3 downto 0)); + A2_3 : out STD_LOGIC_VECTOR (2 downto 0)); end Fct_2_3; architecture Behavioral of Fct_2_3 is @@ -43,6 +43,7 @@ architecture Behavioral of Fct_2_3 is signal shifted_twice : STD_LOGIC_VECTOR(3 downto 0); signal shifted_thrice : STD_LOGIC_VECTOR(3 downto 0); signal carry_out : STD_LOGIC; + signal added : STD_LOGIC_VECTOR(3 downto 0); component Add4Bits is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); @@ -61,10 +62,13 @@ begin -- Both are then added to give the result of the 2/3 multiplication (0.625) result : Add4Bits port map ( - A => "0110", - B => "0001", + A => shifted_once, + B => shifted_thrice, C => '0', - R => A2_3, + R => added, Rc => carry_out ); + + -- The functional specifications require an output of 2 downto 0. MSB would never be 1 anyways. + A2_3 <= added(2 downto 0); end Behavioral; |