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+\begin{verbatim}
+architecture Behavioral of Add1BitB is
+
+begin
+
+Adder: process(X, Y, Ci) is variable buf: STD_LOGIC_VECTOR(2 downto 0);
+begin
+ buf(0) := X;
+ buf(1) := Y;
+ buf(2) := Ci;
+
+ case (buf) is
+ when "000" =>
+ O <= '0';
+ Co <= '0';
+ when "001" =>
+ O <= '1';
+ Co <= '0';
+ when "010" =>
+ O <= '1';
+ Co <= '0';
+ when "011" =>
+ O <= '0';
+ Co <= '1';
+ when "100" =>
+ O <= '1';
+ Co <= '0';
+ when "101" =>
+ O <= '0';
+ Co <= '1';
+ when "110" =>
+ O <= '0';
+ Co <= '1';
+ when "111" =>
+ O <= '1';
+ Co <= '1';
+ when others =>
+ O <= '0';
+ Co <= '0';
+ end case;
+
+end process Adder;
+
+end Behavioral;
+\end{verbatim}