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authorBenjamin Chausse <benjamin@chausse.xyz>2025-05-06 12:40:25 -0400
committerBenjamin Chausse <benjamin@chausse.xyz>2025-05-06 12:40:25 -0400
commit8fd60d09f6f0b63c1b555efbda1242fe9fa39bcc (patch)
tree0f67e1736a249c3810d4030c56051f3bf4739b28 /rapport/assets/code/add1bitb.tex
parent34f74638ca61d1945f616aed7766a5e3ff681468 (diff)
Annex work
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+\begin{verbatim}
+architecture Behavioral of Add1BitB is
+
+begin
+
+Adder: process(X, Y, Ci) is variable buf: STD_LOGIC_VECTOR(2 downto 0);
+begin
+ buf(0) := X;
+ buf(1) := Y;
+ buf(2) := Ci;
+
+ case (buf) is
+ when "000" =>
+ O <= '0';
+ Co <= '0';
+ when "001" =>
+ O <= '1';
+ Co <= '0';
+ when "010" =>
+ O <= '1';
+ Co <= '0';
+ when "011" =>
+ O <= '0';
+ Co <= '1';
+ when "100" =>
+ O <= '1';
+ Co <= '0';
+ when "101" =>
+ O <= '0';
+ Co <= '1';
+ when "110" =>
+ O <= '0';
+ Co <= '1';
+ when "111" =>
+ O <= '1';
+ Co <= '1';
+ when others =>
+ O <= '0';
+ Co <= '0';
+ end case;
+
+end process Adder;
+
+end Behavioral;
+\end{verbatim}