blob: 1ffef11a4229fc12d4404492efcbf4818f492ff9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: BenTheMan
--
-- Create Date: 04/30/2025 01:11:03 PM
-- Design Name:
-- Module Name: full_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder is
Port ( c_in : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
o : out STD_LOGIC;
c_o : out STD_LOGIC);
end full_adder;
architecture Behavioral of full_adder is
signal aXb : STD_LOGIC;
begin
aXb <= a xor b;
o <= aXb xor c_in;
c_o <= (aXb and c_in) or (a and b);
end Behavioral;
|
