1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
\newpage
\appendix
\input{chronographe-bigmama.tex}
\section{Code VHDL}
\begin{figure}[H]
\tiny
\centering
\begin{varwidth}{\linewidth}
\input{assets/code/thermo2bin.tex}
\end{varwidth}
\caption{Module Thermo2bin}
\end{figure}
\begin{figure}[H]
\tiny
\centering
\begin{varwidth}{\linewidth}
\input{assets/code/add4bits.tex}
\end{varwidth}
\caption{Module Add4Bits}
\end{figure}
\begin{figure}[H]
\tiny
\centering
\begin{varwidth}{\linewidth}
\input{assets/code/add1bita.tex}
\end{varwidth}
\caption{Module Add1BitA}
\end{figure}
\begin{figure}[H]
\tiny
\centering
\begin{varwidth}{\linewidth}
\input{assets/code/add1bitb.tex}
\end{varwidth}
\caption{Module Add1BitB}
\end{figure}
\section{Schémas Bloc}
\begin{figure}[H]
\centering
\includegraphics[width=\textwidth]{assets/img/schematic-thermo2bin.png}
\caption{Module Thermo2bin}
\end{figure}
\begin{figure}[H]
\centering
\includegraphics[width=.6\textwidth]{assets/img/schematic-add4bits.png}
\caption{Module Add4Bits}
\end{figure}
\begin{figure}[H]
\centering
\begin{subfigure}{0.60 \linewidth}
\centering
\vfill
\includegraphics[width=\textwidth]{assets/img/schematic-add1bita.png}
\caption{Add1BitA: Conception parallèle}
\end{subfigure} \hfill
\begin{subfigure}{0.39 \linewidth}
\centering
\includegraphics[width=\textwidth]{assets/img/schematic-add1bitb.png}
\caption{Conception séquentielle avec \textit{CASE}}
\end{subfigure}
\caption{Additionneurs 1 bit}
\end{figure}
\section{Tables de Vérité et Karnaugh}
\begin{table}[H]
\centering
\caption{Table de vérité des Bits}
\label{tab:table-de-vérité-thermométrique-4-bits}
\vspace{.2cm}
\begin{tabular}{llllllll}
\toprule
A & B & C & D & E & F & G & H \\
\midrule
0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 \\
0 & 0 & 1 & 1 & 0 & 0 & 1 & 0 \\
0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 \\
1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 \\
\bottomrule
\end{tabular}
\end{table}
% \begin{figure}[H]
% \centering
% \begin{karnaugh-map}[4][4][1][$D$][$C$][$B$][$A$]
% \manualterms{
% 0,1,2,3,
% 4,5,6,7,
% 8,9,10,11,
% 12,13,14,15
% }
% \implicant{1}{9}
% \implicant{4}{6}
% \end{karnaugh-map}
% \caption{Karnaugh pour le bit $H$}
% \end{figure}
%
\begin{figure}[H]
\centering
\begin{karnaugh-map}[4][4][1][$D$][$C$][$B$][$A$]
\manualterms{
0,1,X,0,
X,X,X,1,
X,X,X,X,
X,X,X,0}
\implicant{1}{9}
\implicant{4}{6}
\end{karnaugh-map}
\caption{Karnaugh pour le bit $H$}
\label{tab:karnaugh-bit-H}
\end{figure}
\begin{figure}[H]
\centering
\begin{karnaugh-map}[4][4][1][$D$][$C$][$B$][$A$]
\manualterms{
0,0,X,1,
X,X,X,1,
X,X,X,X,
X,X,X,0}
\implicant{3}{6}
\end{karnaugh-map}
\caption{Karnaugh pour le bit $G$}
\label{tab:karnaugh-bit-G}
\end{figure}
|
