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\newpage
\appendix
\section{Code VHDL}
\todo{Finish this this}
\begin{figure}[H]
\tiny
\centering
\begin{varwidth}{\linewidth}
\input{assets/code/thermo2bin.tex}
\end{varwidth}
\caption{Module Thermo2bin}
\end{figure}
\begin{figure}[H]
\tiny
\centering
\begin{varwidth}{\linewidth}
\input{assets/code/add4bits.tex}
\end{varwidth}
\caption{Module Add4Bits}
\end{figure}
\begin{figure}[H]
\tiny
\centering
\begin{varwidth}{\linewidth}
\input{assets/code/add1bita.tex}
\end{varwidth}
\caption{Module Add1BitA}
\end{figure}
\begin{figure}[H]
\tiny
\centering
\begin{varwidth}{\linewidth}
\input{assets/code/add1bitb.tex}
\end{varwidth}
\caption{Module Add1BitB}
\end{figure}
\section{Schémas}
\todo{Schéma bloc}\\
\todo{Simulations}
\begin{figure}[H]
\centering
\includegraphics[width=.7\textwidth]{assets/img/schematic-thermo2bin.png}
\caption{Module Thermo2bin}
\end{figure}
\begin{figure}[H]
\centering
\includegraphics[width=.7\textwidth]{assets/img/schematic-add4bits.png}
\caption{Module Add4Bits}
\end{figure}
\begin{figure}[H]
\centering
\includegraphics[width=.7\textwidth]{assets/img/schematic-add1bit.png}
\caption{Module Add1Bit}
\end{figure}
\newpage
\section{Tables de Vérité et Karnaugh}
% \begin{figure}[H]
% \centering
% \begin{karnaugh-map}[4][4][1][$D$][$C$][$B$][$A$]
% \manualterms{
% 0,1,2,3,
% 4,5,6,7,
% 8,9,10,11,
% 12,13,14,15}
% \implicant{2}{10}
% \implicant{4}{13}
% \implicant{12}{10}
% \implicantedge{3}{2}{11}{10}
% \end{karnaugh-map}
% \caption{TEMPLATE NOT GOOD}
% \end{figure}
\begin{figure}[H]
\centering
\begin{karnaugh-map}[4][4][1][$D$][$C$][$B$][$A$]
\manualterms{
0,1,X,0,
X,X,X,1,
X,X,X,X,
X,X,X,0}
\implicant{1}{9}
\implicant{4}{6}
\end{karnaugh-map}
\caption{Karnaugh pour le bit $H$}
\end{figure}
\begin{figure}[H]
\centering
\begin{karnaugh-map}[4][4][1][$D$][$C$][$B$][$A$]
\manualterms{
0,0,X,1,
X,X,X,1,
X,X,X,X,
X,X,X,0}
\implicant{3}{6}
\end{karnaugh-map}
\caption{Karnaugh pour le bit $G$}
\end{figure}
\todo{Verite}\\
\todo{Karnaugh}
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