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\begin{verbatim}
architecture Behavioral of Add4Bits is
signal bufA : STD_LOGIC;
signal bufB : STD_LOGIC;
signal bufC : STD_LOGIC;
component Add1BitA is Port (
X : in STD_LOGIC;
Y : in STD_LOGIC;
Ci: in STD_LOGIC;
O : out STD_LOGIC;
Co: out STD_LOGIC);
end component;
component Add1BitB is Port (
X : in STD_LOGIC;
Y : in STD_LOGIC;
Ci: in STD_LOGIC;
O : out STD_LOGIC;
Co: out STD_LOGIC);
end component;
begin
first : Add1BitB port map (
X => A(0),
Y => B(0),
Ci => C,
O => R(0),
Co => bufA);
sec : Add1BitB port map (
X => A(1),
Y => B(1),
Ci => bufA,
O => R(1),
Co => bufB);
third : Add1BitA port map (
X => A(2),
Y => B(2),
Ci => bufB,
O => R(2),
Co => bufC);
fourth : Add1BitA port map (
X => A(3),
Y => B(3),
Ci => bufC,
O => R(3),
Co => Rc);
end Behavioral;
\end{verbatim}
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