diff options
Diffstat (limited to 'pb_logique_seq.gen/sources_1/bd/design_1/design_1.bxml')
| -rw-r--r-- | pb_logique_seq.gen/sources_1/bd/design_1/design_1.bxml | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/design_1.bxml b/pb_logique_seq.gen/sources_1/bd/design_1/design_1.bxml new file mode 100644 index 0000000..6303a3a --- /dev/null +++ b/pb_logique_seq.gen/sources_1/bd/design_1/design_1.bxml @@ -0,0 +1,54 @@ +<?xml version="1.0" encoding="UTF-8"?> +<Root MajorVersion="0" MinorVersion="39"> + <CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true"> + <Description>Composite Fileset</Description> + <Generation Name="SYNTHESIS" State="STALE" Timestamp="1747242954"/> + <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1747242954"/> + <Generation Name="SIMULATION" State="STALE" Timestamp="1747242954"/> + <Generation Name="HW_HANDOFF" State="STALE" Timestamp="1747242954"/> + <FileCollection Name="SOURCES" Type="SOURCES"> + <File Name="synth/design_1.vhd" Type="VHDL"> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + </File> + <File Name="sim/design_1.vhd" Type="VHDL"> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="design_1_ooc.xdc" Type="XDC"> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="OUT_OF_CONTEXT"/> + </File> + <File Name="hw_handoff/design_1.hwh" Type="HwHandoff"> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="HW_HANDOFF"/> + </File> + <File Name="design_1.bda"> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="HW_HANDOFF"/> + </File> + <File Name="hw_handoff/design_1_bd.tcl"> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="HW_HANDOFF"/> + </File> + <File Name="synth/design_1.hwdef"> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="HW_HANDOFF"/> + </File> + <File Name="sim/design_1.protoinst"> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SIMULATION"/> + </File> + </FileCollection> + </CompositeFile> +</Root> |