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diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v
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index 0000000..0a10ec3
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+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v
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+//------------------------------------------------------------------------
+//--
+//--  Filename      : xlslice.v
+//--
+//--  Date          : 06/05/12
+//-
+//-  Description   : Verilog description of a slice block.  This
+//-                  block does not use a core.
+//-
+//-----------------------------------------------------------------------
+
+`timescale 1ps/1ps
+module  xlslice_v1_0_2_xlslice (Din,Dout);
+
+	parameter DIN_WIDTH  = 32;
+	parameter DIN_FROM = 8;
+	parameter DIN_TO = 8;
+	
+	input [DIN_WIDTH -1:0] Din;
+	output [DIN_FROM - DIN_TO:0] Dout;
+	 
+	assign Dout = Din [DIN_FROM: DIN_TO];
+endmodule
+
+